IOSR Journal of VLSI and Signal Processing (IOSR-JVSP)

Nov - Dec 2014 Vol 4 - Issue 6

Version 1 Version 2 Version 3

Paper Type : Research Paper
Title : Gdi Technique Based Carry Look Ahead Adder Design
Country : India
Authors : Gaddam Naga Durga || D.V.A.N Ravi Kumar
: 10.9790/4200-04610109     logo

ABSTRACT: Low Power design is main object in the Very Large Scale Integration (VLSI) Design Gate Diffusion Input (GDI): a new technique for designing the low power digital circuits. This technique allows reducing the power consumption, propagation delay and area of digital circuits. In this paper, a Full Swing Gate Diffusion Input (FS-GDI) methodology is proposed for designing the low power digital circuits. This proposed technique is applied to a 180 nm technology with 1v supply voltage carry look ahead adder (CLA) using MENTOR GRAPHICS.

Keywords: Pass Transistor Logic, Transmission Gate, GDI, Full Swing GDI, Power Dissipation, Delay.

[1]. N. Weste and K. Eshraghian, principles of CMOS digital design. Reading, MA: Addison-Wesley, pp.304-307.
[2]. A.P. Chandrakasan and R.W. Brodersen, "Minimizing Power Consumption in digital CMOS circuits," Proc. IEEE J. Solid –State circuits, vol.83, pp. 498-523, Apr.1995.
[3]. Arkadiy Morgenshtein, Alexander Fish, and Israel A. Wagner, "Gate Diffusion Input (GDI): A power efficient method for combinational circuits", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol,10, NO. 5, October 2002.
[4]. A.P. Chandrakasan and, S.Sheng, and R.W. Brodersen "Low Power CMOS digital Design," Proc. IEEE J. Solid –State circuits, vol.27, pp. 473-484, Apr.1992.
[5]. W. Al-Assadi, A.P. Jayasumana, and Y.K.Malaiya, " Pass Transistor logic design," Int. J. Electron, vol.70,pp.739-749,1991
[6]. R. Zimmermann and W. Fichtner," low-power logic styles: CMOS versus Pass Transistor Logic ," IEEE J. Solid –State circuits, vol.32, pp. 1079-1090, Jun-1997.

Paper Type : Research Paper
Title : Practical Prototyping of a Home Based Microcontroller Security Outfit
Country : Nigeria
Authors : Dr. Mcchester Odoh || Dr. Ihedigbo Chinedum E.
: 10.9790/4200-04611015     logo

ABSTRACT: Security or the lack of it has become a world topical issue today. It is no more news that with the fast increase in technological innovations, sophistication and rise in crime has also become an issue. This has led to an increased demand for better and more secure ways to protect that which we hold precious. This paper adopted the Structure Systems Analysis and Design Methodology (SSADM) and prototyping with the aims of addressing the security issues. At the same time, it attempts to create a microcontroller controlled pass-worded security door embedded with alarm. The system is expected to go off and alert security personnel whenever a wrong password is inputted for three consecutive times. Based on the structural specifications, if dully implemented, would greatly improve the security condition obtainable.
Keywords: Practical prototyping, microcontroller, technological innovations and password.

[1]. Augarten, Stan (1983). The Most Widely Used Computer on a Chip: The TMS 1000. New Havenand New York: Ticknor &
Fields. pp. 5. ISBN 0-89919-195-9.
[2]. Beck, Leland L. (1996). "2". System Software: An Introduction to Systems Programming. Addison Wesley

[3]. Buah FK (1969). The Ancient World, A new History for Schools and Colleges. Book 1, 2nd Edition. London and Basingstoke:
Macmillian Education Limited.
[4]. Dorf, Richard C.; Svoboda, James A. (2001). Introduction to Electric Circuits (5th ed.), pp. 64-65. New York: John Wiley and Sons,
Inc.. ISBN 0-471-38689-8.
[5]. Federal Financial Institutions Examination Council (2008). "Authentication in an Internet Banking Environment". Retrieved 2012-

Paper Type : Research Paper
Title : Research Designs, Survey and Case Study
Country : India
Authors : Dr. Mcchester Odoh || Dr. Ihedigbo Chinedum E
:  10.9790/4200-04611622    logo

ABSTRACT:In every research effort, the first issue is to define the research problem properly, that is, the problem to be investigated or solved. The next issue is to select the research design. The research design occupies a very< critical point in research since the success of the entire research work depends largely on the research design. It is the structure and planning of the entire approach to a problem for research. Research design answers some crucial questions such as "how was the data collected or generated, and how was it analyzed" In other words, it shows your reader how you obtained your result and why in this study surve research design and case study research designs are discussed.

[1]. Holsti, Ole R. (1996). Content analysis for the social sciences and Humanities (massachussets: Additional wesly publishing
[2]. Ikeagwu, E. K. (1998). Groundwork of research: methods and procedures. (Enugu: Institute of development studies University of
nigeria, enugu campus.
[3]. Leedy, Paul D. (1980). Practical Research: planning and design (new york: macmillan publishing company, inc.)
[4]. Oppenhein, A. N. (1970). Questionnaire design and Attitude measurement (london: Heinemann educational books ltd.)
[5]. palmquist, mike(2005). Survey Research. Colorado state university, department of english.

Paper Type : Research Paper
Title : Coignof vantage of Transistor Stack and Input Vector Control Method in Leakage Current Reduction
Country : India
Authors : Philip c.jose || S.karthikeyan || K.Batri
:  10.9790/4200-04612327    logo

ABSTRACT: Leakage current has become a regime in deep sub micrometer circuits. When we move from one technology generation to another technology generation leakage current component is increasing. Out of the total power dissipation majority is the leakage power. The dominant component of leakage power is sub threshold leakage current. Minimizing leakage current is very important in battery powered applications since the leakage drains the battery when circuit is idle. In this paper a survey is done in such a manner so as to outline what so far has done to reduce the leakage power. The paper is organized in such manner that it gives a brief description about standby leakage mechanisms, various standby leakage reduction techniques and what all are the existing technique's available.

Keywords: Leakage current, Standby leakage, Transistor stack, IVC, PBS, SAT solver

[1]. K. Roy, S. Mukhopadhaya, and H. Mahmoodi- Meimand, "Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits," Proc. IEEE, vol. 91, no. 2, Feb. 2003, pp. 305-327
[2]. A model for leakage control by MOS transistlor stacking Mark C. Johnson Purdue University School of Electrical and Computer Engineering ,DineshSomasekhar Purdue University School of Electrical and Computer Engineering KaushikRoy,Purdue University School of Electrical and Computer Engineering.
[3]. S. Bobba and I. Hajj, "Maximum Leakage Power Estimation for CMOS Circuits," in Proc. of the IEEE Alessandro Volta Memorial Workshop on Low-Power Design, 1999.
[4]. Z. Chen, M. Johnson, L. Wei, and K. Roy, "Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks," in Proc. ISLPED, 1998, pp. 239–244.
[5]. J. Halter and F. Najm, "A gate-level leakage power reduction method for ultra-low-power CMOS circuits," in Proc. of the IEEE 1997 Custom Integrated Circuits Conference, 475-478, 1997.

Paper Type : Research Paper
Title : Optimization of 1D and 2D Cellular Automata for Pseudo Random Number Generator
Country : India
Authors : P.Sudhakar || B.Chinnarao || Dr. M. Madhavi Latha
: 10.9790/4200-04612833     logo

ABSTRACT:In this paper we have implemented 1D binary cellular automata with wrap around at the edges (i.e. a ring). The default update rule used is rule 30 discovered by Stephen Wolfram. Rule 30 is an update rule that when applied to the CA will produce a class III, a periodic, chaotic behavior. The response with respect to rule 2 and rule 90 is also verified on Xilinx Spartan 3E FPGA and this can be applied for modeling PRNG. This paper also discusses the correlation between 1D and 2D cellular automata.

[1]. J. Von Neumann, ―The theory of self reproducing Automata‖ (edited by A. W. Burks), University of Illinois Press, Urbana, (1966).
[2]. S. Wolfram, ―Statistical Mechanics of Cellular Automata‖ Rev. Mod. Physics Vol. 55 No. 3 pp 601-644 (July 1983)
[3]. W. Pries, A. Thanailakis and H.C. Card, ―Group Properties of Cellular Automata and VLSI applications‖ IEEE Trans. On Computers Vol. 35 No 12, pp 1013 -1024 (1986).
[4]. A. K. Das, ―Additive Cellular Automata: Theory and applications as a Built in self test structure and VLSI applications‖, Ph. D. Thesis, IIT Kharagpur, India (1990)
[5]. N. H. Packard and S. Wolfram, ―Two dimensional Cellular Automata‖ Journal of Statistical physics Vol. 38 No 5/6 pp 901-946 (1985).
[6]. D. R. Chowdhury, I. S. Gupta and P. P. Choudhuri, ―A Class of two dimensional cellular automata and applications in random pattern testing‖, Journal of Electronic Testing: Theory and Applications, Vol. 5 pp 65-80. (1994)
[7]. A. RaoufKhan , P. P. Choudhury ―VLSI architecture of a cellular automata machine‖, Int. Journal Computers and Mathematics with applications, Vol. 33 No. 5 pp79-94, (1997)

Paper Type : Research Paper
Title : Comparative study of Closed loop and Open loop Contrast Enhancement Techniques
Country : India
Authors : Ramkumar. M. U || Kavitha. N. Nair
: 10.9790/4200-04613440     logo

ABSTRACT:The remote sensing images played an important role in all fields such as agriculture, meteorology, geology, education etc. As the rising demand for high quality remote sensing images, contrast enhancement techniques are required for better visual perception and color reproduction. In this paper we explained a comparative study on open loop and closed loop contrast enhancement techniques which use dominant brightness level analysis and adaptive intensity transformation with discrete wavelet transform. Although various histogram equalization methods are proposed in the literature.

[1] R. Gonzalez and R.Woods, Digital Image Processing, 3rd ed. Englewood Cliffs, NJ: Prentice-Hall, 2007.

[2] Y. Kim, Contrast enhancement using brightness preserving bi-histogram equalization, IEEE Trans. Consum. Electron., vol. 43, no. 1, pp. 18, Feb. 1997

[3] S. Chen and A. Ramli, Contrast enhancement using recursive mean separate histogram equalization for scalable brightness preservation, IEEE Trans. Consum. Electron. vol. 49, no. 4, pp. 13011309, Nov. 2003.

[4] H. Demirel, C. Ozcinar, and G. Anbarjafari, Satellite image contrast enhancement using discrete wavelet transform and singular value decomposition, IEEE Geosci. Reomte Sens. Lett., vol. 7, no. 2, pp. 3333337, Apr. 2010.

[5] H. Demirel, G. Anbarjafari, and M. Jahromi, Image equalization based on singular value decomposition, in Proc. 23rd IEEE Int. Symp. Comput. Inf. Sci., Istanbul, Turkey, Oct. 2008, pp. 15.

[6] Eunsung Lee, Sangjin Kim, Wonseok Kang, Doochun Seo, and Joonki Paik, Contrast Enhancement Using Dominant Brightness Level Analysis and Adaptive Intensity Transformation for Remote Sensing Images, IEEE Transactions on Geosciences and remote sensing letters, vol.10,no.1,jan 2013.

Paper Type : Research Paper
Title : Design and Implementation of Flash ADC for Low Power Applications
Country : India
Authors : Ram Prasad J M, Dr. B.S Kariyappa, Ravishankar Holla
: 10.9790/4200-04614146     logo

ABSTRACT:Flash ADC is one of the most preferred architectures for high speed analog-to-digital data conversion applications. The comparator is a building block of virtually all analog-to-digital converter architecture. The kickback noise in the comparator is one of the important factor which leads to power dissipation. Hence the objective of this project is to design and implement a 4 bit Flash ADC by using effective comparator which reduces the kick back noise. Reduction of the kickback noise makes it possible to drive the ADC with higher impedance, which in turn reduces the power dissipation.

[1] Mohammad Chahardori, Mohammad Sharifkhani and Sirous Sadughi 'A Low-Power 1.2GS/s 4-bit flash ADC in 180-nm CMOS' -2013-IEEE, 2013.

[2] Rajeev Komar, M S Bhat, and TonseLaxminidhi, 'A 0.5V 300uW 50MS/s 180nm 6bit Flash ADC using Inverter Based Comparators', IEEE-International Conference On Advances In Engineering, Science And Management (ICAESM -2012) March 30, 31, 2012.

[3] Pedro M. Figueiredo, and Joao C. Vital, 'Kickback Noise Reduction Techniques for CMOS Latched Comparator', IEEE Transactions On Circuits And Systems—II July 2006.

[4] Ko-Chi Kuo and Chi-Wei Wu 'Capacitive Dynamic Comparator with Low Kickback Noise for Pipeline ADC', IEEE 2013.

[5] Jia Chen, Satoshi Kurachi, Shimin Shen Haiwen Liu, Toshihiko Yoshimasu, Yong JuSuh, 'A Low-Kickback-Noise Latched Comparator for Flash Analog-to-Digital Converters', IEEE2005.

Paper Type : Research Paper
Title : Bio Inspired Fault Tolerance in VLSI Systems – A Survey
Country : India
Authors : Ancy C P
: 10.9790/4200-04614751     logo

ABSTRACT: Living in a Digital age, where each and every small to large things rely upon Electronics, we cannot afford to have unreliable products no matter how small the applications be. But everything human make is prone to errors even if it is given all his care and attention. But there are some applications where the cost of an error can be so huge that we cannot afford to handle, may be the lives of fellow humans or huge set back in economic terms. In such harsh [space] and hostile [nuclear power plants] environments, we need reliable devices that can survive in the conditions that a human eye and hand cannot reach. And that is where we started to think about building fault tolerant devices inspired from nature. Our nature is blessed with millions or organisms that have complex systems than any man-made devices.

[1]. F. Wang and V. D. Agrawal, "Single event upset: An embedded tutorial," in Proc. IEEE 21st Int. Conf. VLSI Design, Jan. 2008, pp. 429–434.
[2]. Aerospace science and technology dictionary f section
[3]. IEEE TRANSACTIONS ON RELIABILITY, VOL. 42, NO. 2,1993 JUNE "Reliability Growth of Fault-Tolerant Software" Karama Kanoun, Mohamed Kaaniche, Christian BhnesJean-Claude, LaprieJean ArlatL.
[4]. Fault Tolerant and Correction System Using Triple Modular RedundancyShubham C. Anjankar1, Dr. Mahesh T. Kolte2 International Journal of Emerging Engineering Research and Technology Volume 2, Issue 2, May 2014, PP 187-191

Paper Type : Research Paper
Title : Survey on Unified Inter/Intrachip Optical Network for Chip Multiprocessors
Country : India
Authors : Priyanka Rajendran, Dr.Gnana Sheela K
: 10.9790/4200-04615261     logo

ABSTRACT:As modern computing systems become increasingly complex, communication efficiency among and inside chips has become as important as the computation speeds of individual processing cores. Traditionally, to maximize design flexibility, interchip and intrachip communication architectures are separately designed under different constraints. Jointly designing communication architectures for both interchip and intrachip communication could, however, potentially yield better solutions. This paper presents unified inter/intrachip optical network called UNION, for chip multiprocessors (CMPs).

[1]. Xiaowen Wu,Yaoyao Ye, Jiang Xu,Wei Zhang, Weichen Liu(2014),.‖UNION: AUnified inter/intra
[2]. OpticalNetwork for Chip Multiprocessors ― ieee transactions on very large scale integration (vlsi) systems, vol. 22, no. 5,
[3]. Nevin Kırman Meyrem Kırman Rajeev K. Dokania Jos´e F. Mart´ınezAlyssa B. Apsel
[4]. Matthew A. Watkins David H(2006). Albonesi.Leveraging OpticalTechnology in FutureBus-based Chip MultiprocessorsThe 39th Annual IEEE/ACM International Symposium on Microarchitecture .
[5]. Sung Hwan Hwang, Mu Hee Cho, Sae-Kyoung Kang, Hyo-Hoon Park, Han Seo Cho (2006)
[6]. Passively Assembled Optical Interconnection SystemBased on an Optical Printed-Circuit Board, DOI: 10.1109/PS.2006.4350170 Conference: Photonics in Switching,
[7]. Assaf Shacham,Keren Bergman, Luca P. Carloni(2008). Photonic Networks-on-Chip for chip microcontroller. ieee transactions on computers, vol. 57, no. 9.

Paper Type : Research Paper
Title : Performance of low power Domino Circuits using pseudo dynamic buffer
Country : India
Authors : Rajeev Kumar, Maneesh kumar Singh, Vimal Kant Pandey
: 10.9790/4200-04616269     logo

ABSTRACT:this paper proposes a buffer circuit for footed domino logic circuit. It minimizes redundant switching at the output node. This circuit prevents propagation of precharge pulse to the output node during precharge phase which saves power consumption. We have calculated the power consumption, delay and power delay product of proposed circuits and compared the results with existing domino circuit for different logic function, loading condition, clock frequency and power supply.

[1]. Neil H.E. Weste, David Harris, Principles of CMOS VLSI Design: A System Perspective, 3rd ed., Addison-Wesley, 2004.

[2]. Tyler Thorp, Dean Liu, Pradeep Trivedi, Analysis of blocking dynamic circuits, IEEE Transactions on VLSI Systems (2003) 744–749. [3]. Neil. H. E and David. H (2004), "Principle of CMOS VLSI Design: a System Perpective,3rd.", Addison-Wesley.

[4]. Thorp. T, Dean. L and Trivedi . P (2003), "Analysis of blocking dynamic circuits", IEEE Trans. On VLSI Systems,pp.744-749.

[5]. Tang. F and Bermak. A (2012), "Low power TSPC-based domino logic circuit design with 2/3 clock load", Trans. on Energy Procedia , vol no.14,pp.1168-1174.

Paper Type : Research Paper
Title : A Study of JK and T Flip Flops with and without Delay Using QCA
Country : India
Authors : Aditi Bal, Subhashree Basu, Supriyo Sengupta
: 10.9790/4200-04617076     logo

ABSTRACT: As transistors decrease in size, more and more of them can be accommodated in a single die, thus increasing chip computational capabilities. However, transistors cannot get much smaller than their current size. The use of quantum dots instead of CMOS transistors for implementing digital system at nanolevel is becoming more and more popular because of its faster speed, smaller size and low power consumption. Many interesting QCA-based logic circuits with smaller feature size, higher operating frequency, and lower power consumption than CMOS have been presented, even though the design of logic modules in QCA is not always straightforward. In this paper, the basic sequential logic structures-JK and T flip-flops are discussed based on QCA design, with comparatively less number of cells and area.

[1] J a'Ja', S.M.Wu.," A new approach to realize partially symmetric unctions". Tech.Rep. SRCTR86-54, Dept.EE, University of Maryland, 1986.

[2] C. S. Lent, P. D. Taugaw, W. Porod , G. H. Berstein.," Quantum Cellular Au- tomata.Nanotechnology", vol. 4, no. 1, pp49-57,January 1993.

[3] A. O. Orlov, I. Amlani, G. H. Bernstein, C. S. Lent, G. L.Sinder.," Realization of a Functional Cell for Quantum Dot Cellular Automata", Science, vol. 277, no. 5328, pp 928-930,August 1997.

[4] C. S. Lent, P. D. Taugaw." A Device Architecture for Computing with Quantum Dots", Proceedings IEEE, vol. 85, no. 4, pp.541-557,April 1997

[5] I. Amlani, A. O. Orlov, G. Toth, C. S. Lent, G. H. Bernstein, G. L.Sinder.," Digital Logic Gate using Quantum Dot Cellular Automata", Science, vol. 284, no. 5412, pp. 289-291,April 1999.

[6] G.Snider, A. Orlov, I Amlani, G. Bernstein, C. Lent, J. Merz and W . Porod, "Quantum- Dot Cellular Automata," Microelectronic Engineering, Vol 47, pp 261-263, 1999

Paper Type : Research Paper
Title : Optimization of Conventional FIR Filter Structures
Country : India
Authors : Rahul Mhatre, Suraj Malpani, Alok Dadlani, Sanchay Srivastava
: 10.9790/4200-04617783     logo

ABSTRACT: FIR Filter Technology has evolved as an eminent technology which has revolutionized the world of Digital Signal Processing (DSP). In addition, the characteristics of a digital filter can be easily changed under software control making them versatile. The research done in this paper focuses on the drawbacks of the given conventional structures and proposes a method to improvise them.

[1] Richard Lyons, Understanding Digital Signal Processing, vol. 1(Addison-Wesley Reading, MA, 1997)
[2] Alan Oppenheim and Ronald Schafer, Discrete-Time Signal Processing, vol. 1(Prentice Hall, EngleWood Cliffs, NJ, 1999).
[3] Vahid, Frank, Digital Design (Hobiken, NJ: Wiley, 2006. Print)
[4] Sonika Gupta, Aman Panghal, Performance Analysis of FIR Filter Design by Using Rectangular, Hanning and Hamming Windows Methods, International Journal of Advanced Research in Computer Science and Software Engineering, Volume 2, Issue 6, June 2012

Paper Type : Research Paper
Title : A Novel Approach for Maternal and Fetal R- Peaks Detection
Country : Egypt
Authors : Mohamed Adel hammad, Mina Ibrahim, Mohiy Mohamed Hadhoud
: 10.9790/4200-04618490     logo

ABSTRACT:The electrocardiogram (ECG) signal is one of the new trends techniques for human identification and authentication. So detecting all waves that formed this signal is very important for human identification and authentication. This research work proposes a new algorithm for detecting most of ECG signals like the signals that have positive R-peaks, the signals that have negative R-peaks and the signals that have positive and negative R-peaks. The proposed algorithm is used for detecting R-peaks from maternal and fetal ECG signals. Recently various algorithms addressed this issue.

[1] Pan, W. I. Tompkins, 1985. A Real-Time QRS Detection Algorithm, (IEEE Trans. Biomed. Eng). vol 32, pp. 230-236.
[2] Qing Chen, Jicheng Liu, Guoliang Li, 2010. "QRS wave Group Detection Based on B-Spline Wavelet and Adaptive Threshold", (International Conference on Computer, Mechatronics, Control and Electroni Engineering) (CMCE).
[3] E.C. Karvounis, C. Papaloukas, D.I. Fotiadis, L.K. Michalis, 1996. "Fetal Heart Rate Extraction From Composite Maternal ECG Using Complex Continuous Wavelet Transform". IEEE computer in cardiology. 31:737-740.
[4] C.W. Li, C.X.Zheng, C.F.Tai, January 1995. Detection of ECG Characteristic Points Using Wavelet Transforms. (IEEE Transaction on Biomedical Eng., 42.No.1:22-28.)
[5] J.S.Sahambi, S.N.Tandon, and R.K.P.Bhatt, 1997. Using Wavelet Transforms for ECG characterization. (IEEE Engineering in Medicine and Biology, 77-83).
[6] Faezipour, M. Tiwari, T.M. Saeed, A. Nourani, M.Tamil, L.S, 2009. Wavelet Based Denoising and Beat Detection of ECG Signal. (Life Science Systems and Applications Workshop. LiSSA 2009.IEEE/NIH, 100-103.)

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