IOSR Journal of VLSI and Signal Processing (IOSR-JVSP)

Jul. - Aug. 2017 Vol 7 - Issue 4

Version 1 Version 2

Paper Type : Research Paper
Title : Measuring the Effects of Rational 7th and 8th Order Distortion Model in the Region of Digital Video Watermarking
Country : India
Authors : Yogesh Verma || Manjit Singh
: 10.9790/4200-0704010108     logo

ABSTRACT: One of the biggest and important issues in the video watermarking is the distortion and attacks. The attacks and distortion affect the digital watermarking. Watermarking is an embedding process. With the help of watermarking, we insert the data into the digital objects. There are few methods are available for authentication of data, securing/protection of data. The watermarking technique also provides the data security, copyright protection and authentication of the data. Watermarking provides a comfortable life to authorized users. In my proposed work, we are working on distorted watermarked video. The distortion is present on the watermarked video is rational 7th and 8th order distortion model...........

Keywords: Video watermarking, Rational 7th and 8th distortion model, Correlation, SSIM, MSE, BER.

[1] V.M. Potdar, S. Han, and E. Chang, "A Survey of Digital Image Watermarking Techniques", INDIN '05. 2005 3rd IEEE International Conference on Industrial Informatics, 2005, pp. 709- 716, 2005.
[2] P. Singh, R.S. Chadha, "A Survey of Digital Watermarking Techniques, Applications and Attacks" International Journal of Engineering and Innovative Technology, vol. 2, no.9, pp. 165- 175, 2013.
[3] G.S. Bhatia, K. Kaur, "Video Watermarking using YcbCr and RLE", International Journal of Engineering and Technology, vol. 03, no.08, pp. 1025- 1030, 2016.

[4] D. Claus and A.W. Fitzgibbon, "A Rational Function Lens Distortion Model for General Cameras", Computer Vision and Pattern Recognition, 2005. CVPR 2005. IEEE Computer Society Conference on", Volume 1, Pages 213-219, July 2005.

[5] A. Agrawal, "Securing Video Data: A Critical Review", International Journal of Advanced Research in Computer and Communication Engineering, vol. 3, no.5, pp6610-6613, 2014.

Paper Type : Research Paper
Title : Design of Low Voltage D-Flip Flop Using MOS Current Mode Logic (MCML) For High Frequency Applications with EDA Tool
Country : India
Authors : Kiran Kumar Mandrumaka || Dr. Fazal Noorbasha
: 10.9790/4200-0704010914     logo

ABSTRACT: This paper presents a new topology to implement MOS current mod logic (MCML) tri-state buffers. In Mos current mode logic (MCML) current section is improves the performance and maintains low power of the circuit. MCML circuits contains true differential operation by which provides the feature of low noise level generation and static power dissipation. So the amount of current drawn from the power supply does not depends on the switching activity. Due to this MOS current mode logic (MCML) circuits have been useful for developing analog and mixed signal IC's. The implementing of MCML D-flip flop and Frequency divider done by using MCML D-latches.............

Keywords: Mos current mode logic (MCML), Tri-state buffer, D-latch, D-flip flop, low power.

[1]. Tajalli A, Vittoz E.,Leblebici Y, Brauer E.J. "Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept" Solid State Circuits Conference.IEEE International Conference,sept -2007 Pages:304 – 307.

[2]. Sumathi,M. "Performance and analysis of cml logic gates and latches"Microwave,Antenna,Propagation and EMC Technologies for Wireless Communications, IEEE International Conference pages: 1428 – 1432,Aug-2007.

[3]. Ni Haiyan ; Hu Jianping , "The layout implementations of high-speed low-power MCML cells"Electronics, Communications and Control (ICECC),IEEE International Conference Page(s): 2936 – 2939, sept-2011.
[4]. H. Knapp, H.-D. Wohlmuth, M. Wurzer, et al., "25GHz Static Frequency Divider and 25Gb/s Multiplexer in 0.12 μm CMOS," ISSCC Dig.Of Tech. Papers, pp. 302-468, Feb.2002.
[5]. M. Tie bout, "A 480μW 2GHz ultra low power dual-modulus prescaler in μm standard CMOS," IEEE International Symposium on Circuitsand Systems Proceedings, vol. 5, pp. 741-744, May. 2000.

Paper Type : Research Paper
Title : Implementation of Area & Power Optimized VLSI Circuits Using Logic Techniques
Country : India
Authors : M.Sivakumar || S.Omkumar
: 10.9790/4200-0704011523     logo

ABSTRACT: To achieve the reduction of power consumption, optimizations are required at various levels of the design steps such as algorithm, architecture, logic and circuit & process techniques. This paper considers the two logic level approaches for low power digital design. Optimization techniques are carried to reduce switching activity power of individual logic-gates. we can reduce the power by using either circuit level optimization or logical level optimization............

Keywords: PASTA, Modified GDI logic, Optimized XOR and half adder, MVL, Tanner toolv14.11.

[1] Arkadiy Morgenshtein, Viacheslav Yuzhaninov, Alexey Kovshilovsky and Alexander Fish, "Full-Swing Gate Diffusion Input logic-Case-study of low-power CLA adder design", Integration, theVLSI journal, Vol. 47, 62-70, 2014.
[2] Basant Kumar, M. and Sujit Kumar, P., "Area-Delay-Power Efficient Carry-Select Adder", IEEE Transactions on Circuits and Systems-II: Express Briefs, Vol. 61, No. 6, June 2014.
[3] Geetha Priya, M. and Baskaran, K., "Low Power Full Adder with Reduced Transistor Count". International Journal of Engineering Trends and Technology (IJETT)-Volume 4 No. 5, May 2013.
[4] Kalavathidevi, T. and Venkatesh, C., "Gate Diffusion Input (GDI) Circuits Based Low Power VLSI Architecture for a Viterbi Decoder", Iranian Journal of Electrical and Computer Engineering (ACECR), Vol. 10, No. 2, 2011.
[5] Kapil Mangla and Shashank Saxena, "Analysis of Different CMOS Full Adder Circuits Based on Various Parameters for Low Voltage VLSI Design", International Journal of Engineering and Technical Research (IJETR), Vol. 3, No-5, May 2015.

Paper Type : Research Paper
Title : PCIe BUS: A State-of-the-Art-Review
Country : India
Authors : Anuj Verma || Pawan Kumar Dahiya
: 10.9790/4200-0704012428     logo

ABSTRACT: PCI Express (Peripheral Component Interconnect Express) abbreviated as PCIe or PCI-E, is designed to replace the older PCI, PCI-X, AGP standards. We present a data communication developed system for use the transfer data between the host and the peripheral devices via PCIe. The performance and the available area on the board are effective by using the PCIe. PCIe is a serial expansion bus interconnection method which is use for high speed communication............

Keywords: PCIe, AGP, PCI-X, PCI

[1]. The NI website [online]. Available:
[2]. The website [online] Available:
[3]. Hossein Kavianipour, Steffen Muschter, Christian Bohm, "High Performance FPGA-Based DMA Interface for PCIe", IEEE Transactions on Nuclear Science, vol.2, pp no. 745-750, April 2014.
[4]. Hossein Kavianipour, Christian Bohm, "High Performance FPGA- Based Scatter/Gather DMA Interface for PCIe", IEEE Nuclear Science Symposium and Medical Imaging Conference Record (NSS/MIC), pp no. 1517-1520, 2012.
[5]. K. Harish, H.S. Aravina, "Development of 8-lane PCI-Express Protocol using VHDL", International Journal Advanced Networking and Applications, vol. 3, pp no. 1169-1175, 2011.

Paper Type : Research Paper
Title : Network-on-Chip: A State-of-the-art Review
Country : India
Authors : Seema || Pawan Kumar Dahiya
: 10.9790/4200-0704012935     logo

ABSTRACT: Large scale System-on-Chip (SoC) has been enabled by the scaling of microchip technologies. As data intensive applications have emerged and processing power has increased, the threat of the communication components on single-chip systems introduced network on chip (NoC). NoC provides the concept of interachip communication. In this paper a study treats an outstanding concept for system-on-chip communication introduced as communication network on-chip (NoC). This paper includes the NoC basics, network topology, relevant research issues and different abstraction levels............

Keywords: NoC, SoC, FPGA, VLSI.

[1] TOBIAS BJERREGAARD AND SHANKAR MAHADEVAN, "A Survey of Research and Practices of Network-on-Chip," ACM Computing Surveys, Vol. 38, March 2006, Article 1.
[2] MUTTERSBACH, J., VILLIGER, T., AND FICHTNER, W. 2000. Practical design of globally-asynchronous locally synchronous systems. In Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC). IEEE Computer Society, 52–59.
[3] BJERREGAARD, T. 2005. TheMANGOclockless network-on-chip: Concepts and implementation. Ph.D. thesis, Informatics and Mathematical Modeling, Technical University of Denmark, Lyngby, Denmark.
[4] RADULESCU, A., DIELISSEN, J., GOOSSENS, K., RIJPKEMA, E., ANDWIELAGE, P. 2004. An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration. In Proceedings of Design, Automation and Testing in Europe Conference (DATE). IEEE, 878–883.
[5] OST, L., MELLO, A., PALMA, J., MORAES, F., AND CALAZANS, N. 2005. MAIA—a framework for networks on chip generation and verification. In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE.

Paper Type : Research Paper
Title : Lowering Power Delivery Issues in 3D-IC
Country : India
Authors : Priya Verma
: 10.9790/4200-0704013638     logo

ABSTRACT: Scaling of transistor size has provided new possibilities in VLSI industry. 3D IC opens door to tremendous applications. The major concern in 3D IC is power dissipation which occurs both in static and dynamic mode of operation. The major parameters on which the power consumption depends on are the supply voltage, clock frequency, die Area, Feature size and number of gates. We have taken the parameters in such a way so that our power consumption got reduced to a lesser amount. we aim to showcase a flow to tackle this problem with following parameters.

[1] N. S. Kim et al., "Leakage Current: Moore's Law Meets Static Power," IEEE Computer, Vol. 36, Issue 12, pp. 68-75, December 2003.
[2] S. J. Park and M. Swaminathan "Temperature-aware power distribution network designs for 3D ICs and systems" IEEE JOURNAL Electronic Components and Technology Conference (ECTC) , 2015 IEEE 65th.
[3] H. Wang and E. Salman, '' Enhancing system-wide power integrity in 3D ICs with power gating" IEEE JOURNAL Quality Electronic Design (ISQED), 2015 16th International Symposium.
[4] Y. J. Lee and S. K. Lim "Co-Optimization and Analysis of Signal, Power, and Thermal Interconnects in 3-D ICs" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems-Nov. 2011.
[5] Dae Hyun Kim and Sung Kyu Lim, " Impact of Through-Silicon-Via Scaling on the Wirelength Distribution of Current and Future 3D Ics" IEEE JOURNAL-2011.

Paper Type : Research Paper
Title : Online Handwritten Text Recognition for Indian Scripts
Country : India
Authors : Ravneet Kaur || Dharam Veer Sharma
: 10.9790/4200-0704013950     logo

ABSTRACT: Online Handwriting Recognition has been a rigorous research area for the last few decades. Substantial amount of work has been reported on the online handwriting recognition of Western, Chinese, Japanese, Korean and Arabic Scripts, but few related to Indian scripts. In this paper a review of online HCR work on almost all popular Indian scripts such as Devanagari, Gurmukhi, Bangla, Tamil, Telugu, Malayalam, Urdu, Kannada, Oriya, and Gujarati is presented.............

Keywords: Online Handwritten text Recognition, Indian Scripts, Character Recognition, OCR, HCR.

[1] U. Pal, B.B. Chaudhuri, "Indian Script character recognition: a survey", Pattern Recognition 37, pp. 1887–1899, 2004.
[2] Soumen Bag, Gaurav Harit, "A survey on optical character recognition for Bangla and Devanagari scripts", Indian Academy of Sciences, pp. 133-168, 2013.
[3] A. Bharath, Sriganesh Madhvanath, "Online Handwriting Recognition for Indic Scripts", Guide to OCR for Indic Scripts, Advances in Pattern Recognition, Springer-Verlag London, pp. 209-234, 2010.
[4] Eric Anquetil and Guy Lorette , "New Advances and New Challenges in On-Line Handwriting Recognition and Electronic Ink Management", Digital Document Processing, Advances in Pattern Recognition, Springer-Verlag London, pp. 143-164, 2007.
[5] S. D. Connell, R. M. K. Sinha and A. K. Jain, "Recognition of unconstrained online Devanagari characters", Proceedings of International Conference on Pattern Recognition, vol. 2, pp. 368-371, 2000

Paper Type : Research Paper
Title : Advance High Performance Bus Arbitration Techniques (AHB): A State-of-the-Art Review
Country : India
Authors : Rinku || Pawan Kumar Dahiya
: 10.9790/4200-0704015156     logo

ABSTRACT: Modern computer system depend more and more on– chip communication protocol to exchange data. System-on-chip (SoC) is designed with reusable intellectual property cores to meet short time to market requirements. The communication delays in the on-chip communication architecture present a major cause of bottlenecks in many SoCs. The selection of the bus (type, width and topology) is one of the most complex tasks of SoC design.AMBA (Advance High Performance Bus) is the best suited bus for this purpose. This paper gives an informative review about the bus interfaces of Advanced Microcontroller Bus Architecture (AHB) and its Arbitration Techniques.

Keywords: Advance Microcontroller Bus Architecture (AMBA), System-on-Chip (SoC), Quality of Service (QoS), Time Division Multiple Access (TDMA)..

[1] ARM, "AMBA Specification Overview", available at
[2] ARM, "AMBA Specification (Rev 2.0)", available at
[3] Anurag Shrivastava, G.S. Tomar and Ashutosh Kumar Singh," Performance Comparison of AMBA Bus-Based System-On-Chip Communication Protocol," International Conference on Communication Systems and Network Technologies , IEEE DOI 10.1109/CSNT.2011.98,p.449.

[4] Sandhya Sunpal and Prof. Mohammed Arif," A Review on High-Performance Microcontroller Bus Architecture," International Journal of Digital Application & Contemporary Research Website: (Volume 4, Issue 2, September 2015).
[5] Benini and D. Bertozzi, "Network-on-chip architectures and design methods," IEEE Proc.-Comput. Digit. Tech., Vol. 152, No. 2, March 2005

Paper Type : Research Paper
Title : Design and Comparison of 8x8 Wallace Tree Multiplier using CMOS and GDI Technology
Country : India
Authors : Pradeep Kumar Kumawat || Gajendra Sujediya
: 10.9790/4200-0704015762     logo

ABSTRACT: Multiplier is an important building block in the design of digital circuits. Multiplier is widely used in Digital signal processing and in communication applications. Compact and small circuit with low power dissipation and very small delay are main desire of circuit designer in the field of VLSI design. A Wallace tree multiplier is an example of improved version of tree base multiplier. Many algorithms have been introduced in the search of the fastest multiplier. There are different types of multiplier based on the algorithm and Wallace tree multiplier is one of them. It uses............ .

Keywords: Multiplier, VLSI Design, Wallace Tree Multiplier, GDI, CMOS.

[1] P.V. Rao, C. P. R. Prasanna, and S. Ravi, VLSI Design and Analysis of Multipliers for Low Power, IEEE Fifth International Conference on Intelligent Information Hiding and Multimedia Signal Processing, Kyoto,2009,pp.1354-1357
[2] C. S. Wallace, A Suggestion for a Fast Multiplier, IEEE Transactions on Computers, 13, 1964, pp.14-17.
[3] Ron S. Waters and Earl E. Swartzlander, "A reduced Comlexity Wallace Multiplier Reduction. IEEE Transactions On Computersl, Vol. 59, No. 8, August 2010.Published by the IEEE computer Society.
[4] A. Daneil Raj, S.Vijayalakshmi and P. Sathyamoorthy," Efficient Design of 4-Bit array multiplier using GDI low power cell", International Journal of Computer Technology and Eectronics Engineein (IJCTEE) Volume2, Issue 6, pp. 47-51,December 2012.
[5] Himanshu Bansal, K. G. Sharma, Tripti Sharma, "Wallace Tree Multiplier Design : A Performance Comparison Review". Innovative Systems Design and Engineering ISSN 2222-2871 Vol.5, No.5,2014.

Paper Type : Research Paper
Title : An Efficient VLSI Architectures for FIR Filter in Fixed and Reconfigurable Applications
Country : India
Authors : D.Bhavani || K. Padma Vasavi
: 10.9790/4200-0704016372     logo

ABSTRACT: Recently, with the development of Software Defined Radio (SDR) technology FIR filters have been concentrated on reconfigurable implementation. The filter coefficients in reconfigurable filters change dynamically in run time. In biomedical applications like Electro Cardio Gram (ECG) the coefficients of FIR filters remain fixed. So there is need to implement a Reconfigurable and Fixed FIR filter structure to support multi-standard communications. The need for reducing the area............ .

Keywords: Finite Impulse Response (FIR) filters, MCM, Transpose-form, VLSI..

[1] J. G. Proakis and D. G. Manolakis, Digital Signal Processing: Principles, Algorithms and Applications. Upper Saddle River, NJ,
USA:Prentice-Hall, 1996.
[2] J. Mitola, Software Radio Architecture: Object-Oriented Approaches to Wireless Systems Engineering. New York, NY, USA: Wiley, 2000.
[3] P. K. Meher, S. Chandrasekaran, and A. Amira, "FPGA realization of FIR filters by efficient and flexible systolization using distributed arithmetic," IEEE Trans. Signal Process., vol. 56, no. 7, pp. 3009–3017,Jul. 2008.
[4] P. K. Meher, "New approach to look-up-table design and memory based realization of FIR digital filter," IEEE Trans. Circuits
Syst. I, Reg. Papers, vol. 57, no. 3, pp. 592–603, Mar. 2010.
[5] J. Park, W. Jeong, H. Mahmoodi-Meimand, Y. Wang, H. Choo, and K. Roy, "Computation sharing programmable FIR filter for low- power and high-performance applications," IEEE J. Solid State Circuits, vol. 39, no. 2, pp. 348–357, Feb. 2004.

Paper Type : Research Paper
Title : Dual-threshold Single-ended Schmitt-Trigger Based Radiation Hardened memory Design with Fault modeling System
Country : India
Authors : Ganesh Chokkakula || Naresh.Kand || Sagar Reddy.V
: 10.9790/4200-0704017380     logo

ABSTRACT: Up to 70% of Systems on a Chip (SoC) area are occupied by embedded memories. Efficient SoC is developed by making memory efficient in terms of power consumption, de-sensitized to environmental changes, Speed and Fault free. Ultra low Power module can be developed by scaling Supply Voltage which leads to loss of stability because of reduced SNM and Switching Threshold levels and this problem can be rectified by introducing Single ended and Schmitt trigger topology to memory cell, which exhibits high read and hold SNM and consumes low power during the hold operation............ .

Keywords: BICS, Weak cell fault model, data retention fault

[1]. A. P. Chandrakasan, D. Daly, J. Kwong, and Y. K Ramadass, "Next generation micro-power systems," in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2008, pp. 2–5.
[2]. P. Macken, M. Degrauwe, M. V. Paemel, and H. Oguey, "A voltage reduction technique for digital systems," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 1990, pp. 238–239.
[3]. S. Borkar, "Obeying Moore's law beyond 0.18 micron, microprocessor design," in Proc. IEEE Int. ASIC/SOC Conf. Sep. 2000, pp. 26–31.
[4]. A. Wang, A. Chandrakasan, and S. Kosonocky, "Optimal supply and threshold scaling for subthreshold CMOS circuits," in Proc. IEEE Computer Society Annual Symp. VLSI, Apr. 2002, pp. 7–11.
[5]. M. E. Sinangil, N. Verma, and A. P. Chandrakasan, "A reconfigurable 65 nm SRAM achieving voltage scalability from 0.25–1.2 V and performance scalability from 20 kHz- 200 MHz," in Proc. European Solid- State Circuits Conf. (ESSCIRC), Sep. 2008, pp. 282–285.

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