IOSR Journal of VLSI and Signal Processing (IOSR-JVSP)

Jul - Aug 2016 Vol 6 - Issue 4

Version 1 Version 2

Paper Type : Research Paper
Title : AES Implementation on Virtex-6 FPGA for Enhanced performance using pipelining and partial reconfiguration techniques
Country : India
Authors : K Navatha || Dr. J.Tarun Kumar || Pratik Ganguly

ABSTRACT:Implementation of Encryption Standard system (AES) by efficient code optimization and partial reconfiguration techniques has been presented in this paper. 128 bit block size and cipher key have been used for this AES implementation. Rijndael algorithm which is also referred as AES is mainly used for ensuring transmission channels security. Xilinx design tool 13.3 and Xilinx project navigator tools are used for synthesis and simulation purpose.For coding of the design, VHDL language has been used. Pipelined design has been implemented on Virtex 6 FPGA device and a throughput of 49.3Gbits/s is achieved with the frequency of 384.793 MHz

Keywords:pipelined design, AES, FPGA, throughput

[1]. Peter J. Ashenden, “The Designer’s guide to VHDL”,2 nd Edition ,San Francisco, CA, Morgan Kaufmann, 2002.

[2]. FIPS 197, “Advanced Encryption Standard (AES)”, No vember 26, 2001.

[3]. A.J. Elbirt et al.,”An FPGA implementation and Performance Evaluatio n of the AES block cipher Candidate Algorithm Finalists”, The Third Advanced Encryption Standard (AES3) Candidate Conference New York,USA,2000.

[4]. Nation Institute of Standards and Technology (NIST), Data Encryption Standard (DES), National Technical Information Service, Sprinfield, VA 22161, Oct. 1999

[5]. A J. Daemen and V. Rijmen , “AES Proposal: Rijndae l”, AES Algorithm Submission, September 3, 1999


Paper Type : Research Paper
Title : HOG & Sparse Based Face Recognition System
Country : India
Authors : Shahina || Arun P.S

ABSTRACT: Face detection and recognition is one of the most challenging problems in the field of image processing. One of the recent techniques in face recognition is by the sparse representation. In this paper, combination of Sparse and Histogram of Oriented Gradients (HOG) are used. In the first stage dimensionality reduction is done to reduce the amount of random variables and the features are extracted using Principal Component Analysis (PCA)........

Keywords: Face Recognition, Sparse Representation, Histogram of Oriented Gradient, Principal Component Analysis

[1]. W.Zhao,R. Chellappa, P. J.Phillips, and A. Rosenfeld,"Face Recognition: A Literature Survey," ACM Computing Surveys, 35(4), pp. 399-458, 2003.
[2]. Jayavel J and Shahnazeer C K "Sparse Representation for Face Recognition" IJCSNS International Journal of Computer Science and Network Security, VOL.14 No.7, July 2014
[3]. A. Yang, J. Wright, Y. Ma, and S. Sastry, "Feature selection in face recognition: A sparse representation perspective," UC Berkeley Tech Report UCB/EECS-2007-99, 2007
[4]. E. J. Candes, X. D. Li, Y. Ma, and J. Wright, "Robust principal component analysis?" J. ACM, vol. 58, no. 1, pp. 1–37, 2011.
[5]. A. Yang, A. Ganesh, Z. Zhou, S. Sastry, and Y. Ma. Fast 𝑙1-minimization algorithms and an application in robust facerecognition: a review. Technical Report UCB/EECS-2010-13,UC Berkeley, 2010.


Paper Type : Research Paper
Title : Epidermal Flexible Printable Non Contact Autonomous ECG Sensor Medical Device Patch for Early Warning
Country : India
Authors : Er M Sesha Giri Rao || Dr V S Chouhan

ABSTRACT: Flexible biosensor based wearable medical devices can act as excellent terminals in the body area electronics of health monitoring system. Benefiting from the growing advancement of electronics and communication technique are wearable medical devices, which can be worn by people and measure physiological parameters like Electro Cardio Gram (ECG), make it possible to monitor the health status continuously to observe deterioration if any, on-line basis, without causing any discomfort to the subjects or patients, in their daily life and could provide warning, even during sleep and wake up the Cardio Vascular or sleep apnea patients.........

Keywords: TFT, Flexible Biosensor, ECG , Printable Electronics, Body Area Electronics

[1] Bahman Kheradmand-Boroujeni et al., "Analog Characteristics of Fully Printed Flexible Organic Transistors Fabricated With Low-Cost Mass-Printing Techniques" IEEE Trans. Electron Devices, vol. 51, no. 5, pp 1423-1430, May 2014
[2] A.C. Hubler et al., "Fully mass printed loudspeakers on paper" Organ. Electron., vol. 13, no. 11, pp. 2290-2295, Nov. 2012
[3] S H Kim et al. "Ink-jet printed organic thin-film transistors for low-voltage driven CMOS circuits with solution processed AlOx gate insulator", IEEE Electron Device Lett, vol. 34, no. 2 pp 307-309, Feb 2013
[4] Yingzhe Hu et al. "Large-Scale Sensing System Combining Large Area Electronics and CMOS ICs for Structural- Health Monitoring", IEEE Journal of Solid State Circuits, vol. 49, no. 2, Feb 214
[5] R Shabanpour et al. Technische Universitat Dresden, Germany and N Munzenrieder et al. Swiss Federal Institute of Technology, Zurich, Switzerland "A Fully Integrated Audio Amplifier in Flexible a-IGZO TFT Technology for Printed Piezoelectric Loudspeakers", 2015 European Conference on Circuit Theory and Design (ECCTD)


Paper Type : Research Paper
Title : An Energy-Efficient sense amplifier using 180nm for SRAM
Country : India
Authors : Meenakshi Thakur || Rajesh Mehra

ABSTRACT: Static Random Access memories are scaled down in order to improve overall density of the chip and hence to lower the power consumption of the system. So increased density but less power consumption optimises the overall system. For SRAM sense amplifiers which are important peripheral circuitry also need to be designed to optimize overall system. Scaling and process variations may change the sense amplifier characteristics which further results to the wrong decision. It has been observed that the threshold variation gives rise to the power and delay variations.........

Keywords: Offset cancellation, static random access memory (SRAM), threshold voltage mismatch, Voltage sense amplifier.

[1] K. Zhang, K. Hose, V. De, and B. Senyk, The scaling of data sensing schemes for high speed cache design in sub-0.18 μm technologies, VLSI Symposium Technical Digest, pp. 226–227,2000.
[2] S. Mukhopadhyay et al., Statistical design and optimization of SRAM cell for yield enhancement, International Conference on Computer Aided Design , pp. 10–13,2004.
[3] M. H. Abu-Rahma et al.,A methodology for statistical estimation of read access yield in SRAMs, Design Automation Conference, pp. 205–210,2008.
[4] Jaspal Singh Shah, David Nairn and Manoj Sachdev, An Energy- Efficient Offset-Cancelling Sense Amplifier, IEEE Transaction on circuit and systems -II, Vol. 60, No. 5,pp. 477-481, Aug. 2013.
[5] Pushpa Saini, Rajesh Mehra, Leakage power reduction in CMOS VLSI circuits, International Journal of Computer Application, Vol. 55, No. 8,pp. 42-47, Oct. 2012.


Paper Type : Research Paper
Title : Optimized Design of Column Level ADC for CMOS Imager using 180 nm Technology
Country : India
Authors : Anurag Yadav || Rajesh Mehra || Deep Sehgal

ABSTRACT: An integrating type ADC is the most commonly used column level ADC for its simple architecture and small surface area. 12-bit Dual slope ADC is developed which has less complexity in design. This architecture has basic advantage that it eliminates the dependence of the conversion on the linearity and accuracy of the slope. The main block of this circuit is opamp. Two stage opamp is developed which has gain of 78dB.........

Keywords: ADC, CIS, CMOS, OPAMP, Pixel

[1]. D. G. Chen, F. Tang, and A. Bermak, A low-power pilot-DAC based column parallel 8b SAR ADC with forward error correction for CMOS image sensors, IEEE Transaction on Circuits System, Vol. 60, No. 10, October 2013, 2572–2583.
[2]. Anjali Sharma, Rajesh Mehra, Area and Power Efficient CMOS Adder Design by Hybridizing PTL and GDI Technique, International Journal of Computer Applications, Vol. 66, No. 4, March 2013, 15-22.
[3]. Pushpa Saini, Rajesh Mehra, Leakage Power Reduction in CMOS VLSI Circuits, International Journal of Computer Applications, Vol. 55, No. 8, October 2012, 42-48.
[4]. Richa Singh and Rajesh Mehra, Power Efficient Design of Multiplexer using Adiabatic Logic, International Journal of Advances in Engineering & Technology, Vol.6, March 2013, 246-254.


Paper Type : Research Paper
Title : FPGA Implementation of Crypto-System based Wireless communication system
Country : India
Authors : Shruthi B || U B Mahadevaswamy

ABSTRACT: Single input and single output (SISO) is the technology in communication and is a new and emerging generation and is predicted to play a completely vital position in 4g Wi-Fi structures. The prototyping of SISO systems through the usage of Field programmable gate arrays (FPGA) or ASIC'S presents an opportunity trying out surroundings for SISO structures[2]. A crucial challenge for the SISO generation will be the design of the transmitter and receiver sections which includes complicated algorithms at each sections[4]..........

Keywords: FPGA, HDL, ISE,SISO.

[1] Figueiras, João, and Simone Frattasi. Mobile positioning and tracking: from conventional to cooperative techniques. John Wiley & Sons, 2011.
[2] Turner, Richard H., and Roger F. Woods. Highly efficient, limited range multipliers for LUT-based FPGA architectures. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 12.10 (2004): 1113-1118.
[3] Leroux, Camille, et al. "Towards Gb/s turbo decoding of product code onto an FPGA device. Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on. IEEE, 2007.
[4] Bölcskei, Helmut. "MIMO-OFDM wireless systems: basics, perspectives, and challenges. Wireless Communications, IEEE 13.4 (2006): 31-37.
[5] Vejdaniamiri, Mehdi. Signal Processing Techniques for Power Efficiency and Signal Quality Enhancement of SISO and MIMO Radio Systems. Diss. University of Calgary, 2014.


Paper Type : Research Paper
Title : Effect of Multi Nutrient on Sweet Orange
Country : India
Authors : Smita R. Chaudhari || A. B. Gawate. || R. S. Chaudhari

ABSTRACT: Sweet orange one of the most important fruit crop. The deterious effect of the nutrient stress lead to reduction in fruit yield and quality of sweet orange. The aim of this paper is to review the current knowledge to evaluate the effect of multinutrient on yield and quality attributes of sweet orange. The result of many works indicates that number of fruits per tree, weight of fruit increased with the application of balanced dose of NPK along with multi micronutrient..........

Keywords: Sweet orange, multi micronutrient, NPK, yield of fruit, quality of fruit.

[1]. Abo El-Komsan EE, Hegab Amera MY, Fouad A (2003). Response of balady Orange trees to foliar application of some nutrients and citric acid. Egypt. J. Agric. Res., NRC-1(1): 73-90.
[2]. Bose, T. K., Mitra, S.K. and Sadhu, M. K. (1988) Mineral Nutrition of Fruits, Kalyani publication Ed.I p. 66,161.
[3]. Brahmachari VS, Yadav GS, Naresh K (1997). Effect of feeding of calcium, zinc and boron on yield and quality attributes of litchi (Litchi chinensis Sonn.). Orissa J. Hort., 25(1): 49-52.
[4]. Deolankar KP, Firake NN (2001). Effect of water soluble fertilizers on growth and yield of banana. J. Maharashtra agric. Univ., 26(3): 333- 334.


Paper Type : Research Paper
Title : Implementation of High-Throughput Digit-Serial Redundant Basis Multipliers over Finite Field
Country : India
Authors : Jyothi Leonore Dake || Sudheer Kumar Terlapu

ABSTRACT: In elliptical curve cryptography the redundant basis (RB) multipliers for finite field have achieved immense popularity. The high-throughput multipliers are presented and they utilize redundant representation. In this paper, a novel recursive decomposition algorithm is presented for digit-level RB multiplication to obtain digit-serial implementation. The signal-flow graph (SFG) is extended to obtain the processor- space flow graph (PSFG) and also to acquire the three novel multipliers. Implementation of 10 bit digit-serial RB multipliers is presented in this work. The proposed structures are simulated and synthesized in Xilinx 12.2 using Verilog HDL.

Keywords: Cryptography, Digit-serial multiplication, finite field, redundant representation.

[1]. H.Niederrieter,Introduction to finite fields and their applications 2nd edition (Cambridge,UK:Cambridge University Press, 1997).
[2]. Swamy.M.N, Cryptography applications of bhaskara equations,IEEE Trans.Circ.Sys.I, vol.54 (7), 2007, 927-928.
[3]. Retheesha.D and Ajitha.S.S, Efficient implementation of bit parallel finite field multipliers, IJRET,vol 3, 2014, 661-667.
[4]. Jun-CheolJeon and Kee-W.Kim, Finite field arithmetic architecture based on cellular array,International Journal of Cyber-Security Forensis, 1(2), 2012,122-129.
[5]. L.S.Hsu, Comparison of VLSI architecture of finite field multipliers using dual, normal or standard basis,IEEE Trans.Comp., 1987,63-75.


Paper Type : Research Paper
Title : Fault Detection and Diagnosis
Country : India
Authors : S Vinayaka Babu || K V Ramana Reddy || Siva S Yellampalli

ABSTRACT: This paper describes about the ability of a system to detect the fault and diagnose of the test board by using generic logic array (GAL). It has been very popular in defense sectors like military systems, aerospace and medical instruments as well as in security and safety applications. The methodology used in this is "repair on the go" which detects the fault IC on the board that is under the test, then that fault IC is controlled by one of the columns of GAL. The fault pin of that IC can be visualized using a seven segment display and audio representation with the help of a buzzer. This method increases the life line of the system and this methodology can also be implemented using FPGA's

[1]. L. Yadav, G. Kaur and K. N, "STUDY OF PROGRAMMABLE LOGIC DEVICES", IJIRT, vol. 112, no. 12, 2015.
[2]. C. Lee, D. Hall, M. Perkowski and D. Jun, "Self-repairable GALs", Journal of Systems Architecture, vol. 47, no. 2, pp. 119-135, 2001.
[3]. "Computer Aid Digital Design", Mazsola.iit.uni-miskolc.hu, 2016. [Online]. Available: http://mazsola.iit.uni-miskolc.hu/cae/docs/theor00.html. [Accessed: 09- Jun- 2016].
[4]. K. S. Son and D. K. Pradhan, "Design of Programmable Arrays for Testability," 1980 IEEE Test Conference, pp.163-166, 1980.
[5]. D. L. Ostapko and S. J. Hong, "Fault Analysis and Test Generation for Programmable Logic Array (PLA)," IEEE Trans. on Computers, Vol. C-28, No. 9, pp.617-627, September 1979


Paper Type : Research Paper
Title : Reaction Time Measurement System for the Assessment of Persons with Auditory Processing Disorder
Country : India
Authors : Hariprasad.B || Shreekanth.T || Ajish.K.Abraham

ABSTRACT: Auditory processing disorder (APD) is a set of problems that occur in different kinds of listening tasks. It is found in children and adults as well. Different methods are used in developed countries for the early detection of APD. Auditory processing disorder (APD) is a set of problems that occur in different kinds of listening tasks. It is found in children and adults as well. Different methods are used in developed countries for the early detection of APD. These methods are not advisable in testing children below 11 years. APD is directly related to the time taken by the person to react to a speech signal. In this paper the reaction time is measured using MATLAB program to find out whether a person can be tested for suspected APD.

Keywords: Auditory Processing Disorder, Reaction time, stimulus, cognition

[1]. Moore DR, Rosen S, Bamiou DE, Campbell NG, Sirimanna T. "Evolving concepts of developmental auditory processing disorder: A British society of Audiography. APD special interest group white paper" .International journal Audiology. Jan 2013
[2]. Melanie Ferguson and Dave Moore. "Diagnosing APD Findings from a population study of auditory processing." MRC Institute of Hearing Research. Nottingham University. UK. 2008
[3]. Sonam Pal; M. Tech Scholar, EC, Department SSSIST, Sehore, India, Jaikaran Singh ; H.O.D and Associate Professor, EC Department, SSSIST, Sehore, India."Analytical Review of Feature Extraction Technique for Automatic Speech Recognition"International Journal of Science and Research (IJSR) NOV 2015
[4]. Nidhi Desai, Prof.Kinnal Dhameliya: Department of Electronics and communication engineering, CGPIT, Bardoli. Prof. Vijayendra Desai: Department Of Electronics and Communication Engineering, C.K.P.C.E.T., Surat."Recognizing voice commands for robot using MFCC and DTW": International Journal for advanced research in computer and communication engineering. May 2014, pp. 6456 – 6459


Paper Type : Research Paper
Title : Adaptive Differential Evolution For Optimal Schedule In Behavioral Level Synthesis
Country : India
Authors : Shilpa K.C || LakshmiNarayan .C || Manoj Kumar Singh

ABSTRACT: This paper presents the adaptive differential evolution for optimal scheduling in Behavioral level synthesis. The benchmark problem for the scheduling problem taken is Hardware Abstraction Layer (HAL) benchmark scheduling problem using Integer Linear Programming method. The adaptive scaling factor for mutation operation in differential evolution is implemented. The experiment results evaluate the performance parameters optimal resource schedule. The exploration and exploitation to global optimal scheduling with minimum convergence time and minimum number of computations are presented.

Keywords: Optimal schedule, evolution computation, differential evolution, hardware abstraction layer, Integer Linear Programming.

[1] De Micheli .G. Synthesis and Optimization of Digital Circuits. USA: McGraw-Hill; 1994. J.
[2] Gajski.D, Dutt N.D, Wu.A, Lin.S." High Level Synthesis: Introduction to chip and System Design",USA:Kluwer Academic Publisher; 1992.
[3] Hwang C.T, Lee J.H, Hsu Y.C, Lin. Y.L. A formal approach to the scheduling problem in high level synthesis. In: IEEE Trans. on Computer-Aided Design. Feb 1991. p. 464-475.
[4] Paulin P.G, Knight J.P. Force-directed scheduling in automatic data path synthesis. In: Proc. of the 24th ACM/IEEE Conference on Design Automation . 1987.p.195–202.
[5] Camposano.R . Path-based scheduling for synthesis. In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 1991. p. 85–93.


Paper Type : Research Paper
Title : Intelligent household led lighting system for energy saving
Country : India
Authors : Miss. Ashwini Deshmukh || Dr. K.B.Khanchandani

ABSTRACT: Daily more and more home appliances and consumer electronics are installed in homes. Residential energy consumption tends to grow rapidly. Around 10 % of a total household power is consumed during standby power mode, the reduction of standby power is greatly necessary to reduce the electricity cost in home. The existing lights cannot be controlled in various ways, it causes unnecessary power consumption. So, the invention of LEDs which have only 50% of the power consumption as compared to fluorescent is expected to help to lessen the energy consumption problem...........

Keywords: Lighting control system ,Led light, Wireless sensor.

[1]. Andreas Foglar, Halid Hrasnica, Maurice Draaijer, Nikolaos Mouratidis, Spyridon Tompros , "Enabling Applicability of Energy Saving Applications on the Appliances of the Home Environment", November/December 2009 , pg no.8-16.
[2]. Haesik Kim, Honggang Zhang, Kari Horneman, Tao Chen, Yang Yang," Network Energy Saving technologies for Green Wireless Access Networks", October 2011, pg no. 30-38.
[3]. Jinsung Byun, Sehyun Park," Development of a Self-adapting Intelligent System for Building Energy Saving and Context-aware Smart Services", Vol. 57, no.1,February 2011, pg no.90-98.
[4]. Jinsoo Han, Chang-Sic Choi, and Ilwoo Lee, "More Efficient Home Energy Management System Based on ZigBee Communication and Infrared Remote Controls",Vol.57, no.1 February 2011,pg. no. 85-89.
[5]. Cagdas Atici, Tanir ozcelebi and Johan J. Lukkien, "Exploring User-Centered Intelligent Road Lighting Design A Road Map and Future Research Directions", Vol.57, no.2, February 2011, pg. no. 788-793.



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