IOSR Journal of VLSI and Signal Processing (IOSR-JVSP)

Sep - Oct 2014 Vol 4 - Issue 5

Version 1 Version 2

Paper Type : Research Paper
Title : Implementation of Transistor Stacking Technique in Combinational Circuits
Country : India
Authors : Ankita Nagar , Vidhu Parmar
: 10.9790/4200-04510105     logo

ABSTRACT: This paper deals with the reduction of power dissipation in the basic logic circuit like NAND gate and NOR gate by using transistor stacking technique. The logic gates are designed using 130nm technology parameter and are simulated using PSPICE. The input vector combinations are compared with the simulated result on the basis of propagation delay and power consumption. It is found that when the number of low-input increases in case of NAND gate the power dissipation decreases but the delay increases and for NOR gate power dissipation decreases with the increase in high input vector combinations.

Index Terms: Low Power, Propagation Delay, Power Dissipation, Sub-threshold current, stacking effect.

[1]. Sylvester, Dennis and Srivatava, Ashish "Computer Aided design for Low- Power Robust Computing in Nanoscale CMOS", Proceedings of the IEEE, Vol. 95, No. 3, pp 507-529, March 2007.
[2]. Kuroda, Tadahiro "Optimization and Control of VDD & VTH for Low Power, High Speed CMOS Design", 2002, department of electrical engineering, Keio University.
[3]. Kuroda, Tadahiro "Variable Supply Voltage Scheme for Low Power High Speed CMOS Digital Design", IEEE Journal Solid States Circuit, Vol. 33-No. 3, pp. 454-462, March 1998.
[4]. Deepak Subramanyan, B.S & Adrian Nunez "Analysis of Sub Threshold Leakage Reduction in CMOS Digital Cirtuits", Proceedings of the 13th NASA VLSI Symposium, June 2007, IDAHO, USA.
[5]. Sreenivasa Rao Ijjada, B. Ramparamesh, "Reduction of Power Dissipation in Logic Circuits", International Journal of Computer Applications, Vol. 29-No. 6, June 2011.


Paper Type : Research Paper
Title : Optimized high performance multiplier using Vedic mathematics
Country : India
Authors : Pradeep M C , Dr. Ramesh S
: 10.9790/4200-04510611     logo

ABSTRACT: Multiplication is the commonly used operations in a Central Processing Unit (CPU). The performance of the CPU depends on multiplier which may be slower and may consume significant amount of power. This work presents a low power and high speed multiplier architecture using Vedic mathematics technique. The work also proves the efficiency of Urdhava Tiryakbhyam sutra of Vedic mathematics which shows a difference between actual process of multiplication and Vedic multiplication. Carry Save Adder (CSA) is used in the architecture to have reduced delay. The proposed multiplier circuit is synthesized using Xilinx 13.1 version tool for Field Programmable Gate Array (FPGA) flow and Cadence 12.10 version tool for Application Specific Integrated Circuit (ASIC) flow for the analysis of dynamic power consumption and propagation delay and the design is simulated using Modelsim 6.5 version tool for functional verification.

Keywords: ASIC flow, CSA, FPGA flow, Vedic mathematics, Urdhava Tiryakbhyam sutra

[1]. Reto Zimmermann, Lecture notes on computer arithmetic: principles, architecture and design (Integrated Systems Laboratory, ETH Zurich, March 1999).
[2]. Sunder S. kidambi, Fayez el-Guibaly and Andreas Antoniou, Area efficient multipliers for digital signal processing applications: IEEE transactions on circuits and systems-II: Analog and Digital Signal Processing, vol. 43, no. 2, February 1996, pp. 90-95.
[3]. Johnny Pihl and Einar J. Aas, A multiplier and squarer generator for high performance DSP applications: IEEE 39th Midwest symposium on Circuits and Systems, Ames, IA, vol 1, 18-21 Aug 1996, pp. 109-112.
[4]. Akhalesh K, Itawadiya, Rajesh Mahle, Vivek Patel and Dadan Kumar, Design a DSP operations using vedic mathematics: IEEE International Conference on Communications and Signal Processing (ICCSP), Melmaruvathur, 3-5 April 2013, pp. 897-902.

[5]. Nick Carter, Schaum's outline of theory and problems of computer architecture (The McGraw-Hill Companies Inc. Indian Special Edition 2009).


Paper Type : Research Paper
Title : Design and Verification of VHDL Code for FPGA Based Slave VME Interface Logic
Country : India
Authors : Manju Mohan , Nishi G Nampoothiri
: 10.9790/4200-04511217     logo

ABSTRACT: Versa Module Europa (VME) bus is used in various applications in order to ensure safety and security. VME64x based Real Time Computer (RTC) system with various types of Input / Output (I/O) hardware modules is being designed and developed for use in various safety critical and safety related Instrumentation & Control (I&C) systems. Analog Output Card (AOC) is one of the I/O hardware modules as part of VME64x RTC development. The AOC uses Field-Programmable Gate Array (FPGA) as VME bus system controller. This paper discusses the design and development of a VME64x bus controller so as to meet the required specifications correctly.

Keywords: A16/A24/D16 Bus interface, Analog Output Card (AOC), Field Programmable Gate Array (FPGA), VHSIC Hardware Description Language (VHDL), VME64x bus

[1]. Field-programmable gate array - Wikipedia, the free encyclopedia.
[2]. Douglas Perry, VHDL Programming (Tata McGraw Hill)
[3]. An American National Standard, IEEE Standard for a Versatile Backplane Bus: VMEbus.
[4]. Understanding metastability in FPGAs, ALTERA.


Paper Type : Research Paper
Title : FPGA Implementation of an Efficient VLSI Architecture for Lift Based 5/3 DWT
Country : India
Authors : Shriram P Hegde , S Ramachandran
: 10.9790/4200-04511823     logo

ABSTRACT: The wavelet transform has emerged as advanced technology in the field of VLSI implementation for image compression. Wavelet based coding provides improvements in picture quality at higher compression ratios. In this paper, we propose an efficient VLSI architecture for lifting based 5/3 DWT using FPGA. The lifting scheme 5/3 algorithm is used for implementing 1D-DWT architecture. The 2D-DWT lifting based architecture is designed using 1D-DWT lifting architectures. The proposed architecture uses less hardware interns of dedicated multipliers compared to existing architectures. The proposed architecture is implemented on Virtex-IV FPGA and it is observed that the parameters such as LUT's and delays are efficient.

Keywords: Discrete Wavelet Transform (DWT), Lifting Schemes, CDF-5/3, 1D-DWT, 2D-DWT etc.

[1] S. Mallat, "A Theory for Multiresolution Signal Decomposition: The WaveletRepresentation", IEEE Transaction on Pattern Analysis and Machine Intelligence, Vol. 11, No. 7, pp. 674-693, 1989.
[2] Durgasowjanya, K.N.H. Srinivas and P. VenkataGanapathi,"FPGA Implementationof efficient VLSI Architecture for fixed point1-D DWT using Lifting Scheme", International Journal of VLSI Design and Communication Systems, Vol.3, No.4, 2012.
[3] Nagabushanam M and Ramachandran S., "Fast implementation of Lifting Based 1D/2D/3D DWT-IDWT Architecture for Image Compression", International journal of computer Applications, Vol. 12, Issue. 11, pp.23-29, 2012.
[4] K. Andra, C. Chakrabarti and T. Acharya ,"A VLSI Architecture for Lifting-Based Forward and Inverse Wavelet Transform," IEEE Transaction on Signal Processing, Vol.50, No.4, pp.966-977, 2002.
[5] Husain K.Bhaldar, V.K. Bairagi and R.B. Kakkeri, "Hardware Design of 2-D High Speed DWT by Using Multiplierless 5/3 Wavelet Filters", International Journal of Computer Applications, Vol. 59, No. 17, pp. 42-46, 2012.


Paper Type : Research Paper
Title : Agricultural Plant Leaf Disease Detection and Diagnosis Using Image Processing Based on Morphological Feature Extraction
Country : India
Authors : Mr. Sachin B. Jagtap , Mr. Shailesh M. Hambarde
: 10.9790/4200-04512430     logo

ABSTRACT: Leaf spots can be indicative of crop diseases, where leaf batches (spots) are usually examined and subjected to expert opinion. In our proposed system, we are going to develop an integrated image processing system to help automated inspection of these leaf batches and helps identify the disease type. Conventional Expert systems mainly those which used to diagnose the disease in agriculture domain depends only on textual input. Usually abnormalities for a given crop are manifested as symptoms on various plant parts. To enable an expert system to produce correct results, end user must be capable of mapping what they see in a form of abnormal symptoms to answer to questions asked by that expert system. This mapping may be inconsistent if a full understanding of the abnormalities does not exist. The proposed system consists of four stages; the first is the enhancement, which includes HIS transformation, histogram analysis, and intensity adjustment. The second stage is segmentation, which includes adaptation of fuzzy c-means algorithm. Feature extraction is the third stage, which deals with three features, namely color size and shape of spot. The fourth stage is classification, which comprises back propagation based neural networks.

Keywords: ANOVA, Classifier, FCM, Feature extraction, Image processing, Leaf disease

[1]. Mohammad El-Helly, Ahmed Rafea, Salwa El-Gammal, "An Integrated Image Expert Processing System for Leaf Disease Detection and Diagnosis", Central Lab. For Agricultural System(CLAES), Agricultural Research Center(ACR), Giza,Egypt
[2]. John Hartman, Brian Eshenaur, "Plant Pathology fact sheet‟, University of Kentucky-college of agriculture,PPFS-GEN-02.
[3]. Report on plant disease, Dept. of crop sciences, University of Illinois at urbana-champaign, RPD NO.705 March 2004.
[4]. Agrios G.N., Plant Pathology (Academic Press, 4th Edition, 1997).
[5]. Sindhuja Sankaran, Ashish Mishra, Reza Ehsani, Cristina Davis, "A review of Advanced techniques for detecting plant disease‟, Computer and electronics in agriculture 72(2010)1-13, 2010.
[6]. Review article, "Innovative tools for detection of plant pathogenic viruses and bacteria‟ Int Microbiology ,6: 233-243, 2003.


Paper Type : Research Paper
Title : A Study on Programmable System on Chip
Country : India
Authors : Abhay Raj Kansal
: 10.9790/4200-04513137     logo

ABSTRACT: PSOC (Programmable System-on-Chip) is a family of integrated circuits made by Cypress Semiconductor. These chips include a CPU and mixed-signal arrays of configurable integrated analog and digital peripherals. A PSoC integrated circuit is composed of a core, configurable analog and digital blocks, a software configured and programmable routing and interconnect.

Keywords: PSoC Designer, PSoC Creator, PSoC 3/5, microcontrollers, Capacitive Sensor, Thermistor, 24 External pins for output.

[1]. Jon Peterson, "Capacitive sensing 101 PSoC 3 and 5 first touch starter kit" Applications Engineer, Cypress Semiconductor Corp. 43674. Oct 2006.
[2]. Andrzej Rucinski "Lecture on PSoC architecture" University of New Hampshire, USA – Oct 2012.
[3]. Patrick Kane "Lecture on introduction to PSoC 3 and capsense", Director Cypress University Alliace, Oct 2012.
[4]. Todd O"Connor, "mTouch projected capacitive touch screen sensing theory of operation", Microchip Technology Inc. TB3064, DS93064A 2010.
[5]. Zack Albus "PCB-based capacitive touch sensing with MSP430" Application Report, SLAA363A – June 2007 – Revised October 2007


Paper Type : Research Paper
Title : Improved Seamless Cloning based Image In painting
Country : India
Authors : Uppuretla Pavan Kumar , T.S.R Krishna Prasad
: 10.9790/4200-04513845     logo

ABSTRACT: Image in-painting is a restoration of image parts which are missing either accidentally or intentionally, and also image recovery is a research hot spot in the computer graphics and computer vision in the current. Two major inpainting techniques are introduced, those are PDE-based and Texture based algorithms. In PDE-based technique a conventional image matching techniques may be classified as either area based or feature based methods. In this paper, taking an input image and apply Pre-processing, After we get gray image and contour extraction algorithm is used to extract the contour features of damaged area, which determine the contour feature location. After that Matching algorithms play a key role in deciding correspondences between two image scenes. Area-based matching algorithm is used to search alternative matching area .Contour-based Similarity Distance function (CSD) is used to determine the most similar matching area. According to the damaged area and the matching area, the source cloning domains and target cloning domains of Seamless Cloning algorithm is improved. Using mean value coordinates to achieve regional pixel cloning from the source cloning domain to the target cloning domain. Finally, the improved SC algorithm is used to repair the image. Experimental results confirm the effectiveness of the proposed algorithm, and that the method can not only repair small-scale scratches, but also repair a large area damaged areas.

Keywords: Contour extraction; Image inpainting; Matching; Seamless cloning

[1]. Shrilaxmi Deshpande &Shalini Bhatia. "Image Inpainting Using Cloning Algorithms" [J] International Journal for Image Processing (IJIP), Volume (6): Issue (6): 2012.
[2]. JyotiJoglekar, Shirish S. Gedam. "Area Based Image Matching Methods"[J].International Journal of Emerging Technology and Advanced Engineering. ISSN 2250-2459, Volume 2, Issue 1, January 2012.
[3]. Joglekar J. V, Gedam S. S., Area Based Image Matching Technique using Haudorff distance and Texture analysis, ISPRS WG III/4 International conference PIA11 , Technical University of Munchen, Germany, 2011.
[4]. Panagiotis Gioannis. "Automatic Contour Extraction from 2D Images" Applied Medical Informatics Original Research, Vol.28, No.1 / 2011. pp: 9-15.
[5]. Zhen Hua, Yewei Li &Jinjiang Li. "Image Inpainting Algorithm based on Contour features and Improved MVSC" [J] International Conference on Computer Design And Applications (ICCDA), Volume (1) ,2010. Pp-212-216.


Paper Type : Research Paper
Title : FPGA Implementation of Viterbi Algorithm for Decoding of Convolution Codes
Country : India
Authors : K.Santhosh Kumar , M.V.H. Bhaskara Murthy
: 10.9790/4200-04514653     logo

ABSTRACT: Convolutional code is a coding scheme used in communication systems including deep space communications and wireless communications. It provides an alternative approach to block codes for transmission over a noisy channel. The block codes can be applied only for the block of data. The Convolutional coding has an advantage over the block codes in that it can be applied to a continuous data stream as well as to blocks of data. Viterbi decoder employed in digital wireless communication plays a rife role in the overall power consumption of trellis coded modulation decoder. Power reduction in Viterbi decoder could be achieved by reducing the number of states. A pre-computation architecture with T-algorithm was implemented for this purpose, and when we compare this result with full Trellis Viterbi decoder, this approach significantly reduces power consumption without degrading decoding speed. Convolutional encoding with viterbi decoding is a powerful FEC technique that is particularly suited to a channel in which the transmitted signal is corrupted mainly by Additive White Gaussian Noise (AWGN). It operates on data stream and has memory that uses previous bits to encode. The Viterbi Algorithm (VA) is proposed, used for decoding a bit stream that has been encoded using FEC code. The Convolutional encoder adds redundancy to a continuous stream of input data by using a linear shift register. A pre-computation architecture with Viterbi algorithm is implemented for this purpose, Viterbi (Convolutional) encoder and Viterbi decoder are designed and implemented using FPGA technology, which are the essential blocks in digital communication systems. It is particularly suited to a channel in which the transmitted signal is corrupted mainly by AWGN. The Viterbi decoder of Constraint length 7 and code rate ½ is considered. The design is implemented using verilog on Xilinx Spartan 3E and advanced Spartan 6 board and the results and Comparisons are presented.
Keywords: Convolutional encoder, FPGA, verilog, Viterbi Algorithm, Viterbi decoder

[1] Montse Boo, Francisco Arguello, Javier D.Bruguera, Ramon Doallo, and Emilio L.Zapata." High-Performance VLSI Architecture for the Viterbi Algorithm". IEEE Trans. Communications, 45(2), February 1997.
[2] F.Arguello, J.D.Bruguera, R.Doallo, and E.L.Zapata. "Parallel Architecture for Fast Transforms with Trigonometric Kernel". IEEE Trans. Parallel and Distributed Systems, 5(10), October 1994.
[3] J. He, Z. Wang, and H. Liu, "An efficient 4-D 8PSK TCM decoder architecture," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 5, pp. 808–817, May 2010.
[4] J. He, H. Liu, and Z. Wang, "A fast ACSU architecture for viterbi decoder using T-algorithm," in Proc. 43rd IEEE Asilomar Conf. Signals,Syst. Comput., Nov. 2009, pp. 231–235.

[5] Jie Jin, Chi-ying Tsui "Parallel state Viterbi decoder implementation based on scarce state transition," IEEE Trans.Very Large Scale Integr. (VLSI) Syst., vol. 15, no. 11, pp. 1172–1176,Oct. 2007


Paper Type : Research Paper
Title : Delay-Power Performance of High Speed Radix 32 Booth Multiplier in 40nm Process Technology
Country : India
Authors : Er.Jatinder Pal Singh , Prof.RupinderKaur , Prof.Vishal Mehta
: 10.9790/4200-04515459     logo

ABSTRACT: Multipliers play an important role in today's digital signal processing and various other applications. With advances in technology, many researchers have tried and are trying to design multipliers which offer either of the following design targets – high speed, low power consumption, regularity of layout and hence less area or even combination of them in one multiplier thus making them suitable for various high speed, low power and compact VLSI implementation This thesis looks into the design and simulations of 32 bit booth multiplier with high speed carry select adder in 40 nm process technology and effect of temperature on power consumption. Process level simulation has been carried out on Xilinx suite 12.3.1 and Model -sim. For Investigation about Power, X Power Analyser is used which shows variation of power with respect to temperature.

Keywords: DSP, CSLA, RCA

[1]. Er. Neha Gupta, Dr. B K Sharma "EMPIRICAL REVIEW OF LOW POWER COLUMN BY PASS MULTIPLIER" International Journal of Computing and Corporate Research ISSN (Online): 2249-054X, Volume 4, Issue 3 May 2014, International Manuscript ID : 2249054XV4I3052014-19
[2]. RubiChoubey, Md. Arif "AREA OPTIMIZED AND LOW POWER USING MODIFIED BOOTH MULTIPLIER FOR UNSIGNED NUMBERS" International Journal of Emerging Science and Engineering (IJESE) ISSN: 2319–6378, Volume-2, Issue-6, April 2014
[3]. Amita P. Thakare, SaurabhAgrawal, VibhaTiwari "32 BIT CARRY SELECT ADDER WITH BEC-1 TECHNIQUE" Proceedings of Sixth IRAJ International Conference, 6th October 2013, Pune, India. ISBN: 978-93-82702-32-0
[4]. Naveen Kumar, Manu Bansal, AmandeepKaur "SPEED POWER AND AREA EFFICENT VLSI ARCHITECTURES OF MULTIPLIER AND ACCUMULATOR" International Journal of Scientific & Engineering Research Volume 4, Issue 1, January-2013 ISSN 2229-5518
[5]. Shweta S. Khobragade and Swapnili P. Karmore "LOW POWER VLSI DESIGN OF MODIFIED BOOTH MULTIPLIER" Int. J. on Recent Trends in Engineering and Technology, Vol. 9, No. 1, July 2013.




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