iosr-JVSP   Volume-3 ~ Issue-3

ABSTRACT:The study was conducted using plantain peel ash and cassava peel ash as an active ingredient. These peels are agricultural waste materials that litter the whole environment. The study used the peels as alternative source to the much needed lye, in soap making. The usage of these peels will reduce the cost of soap making and also reduce waste materials in our environment and these will reduce diseases caused by these waste. The plantain peels and cassava peels were burnt into ashes and the ashes were turned into solution with water and filtered. The filtrate was boiled with palm kernel oil, until good lathering soaps were obtained, sensory evaluation was conducted using 15 home Economic respondents. The data were analyzed using frequency distribution and percentage. The qualities of the soap evaluated were the colour, odour, lathering ability and texture. The findings showed that the ashes were good alternative, ingredient for soap making. Recommendations were made based on the findings: that the use of the raw materials should be encouraged for soap making to save the country's foreign exchange. There is need to create awareness on the use of the ashes. Home economics graduates should exploit the self employment opportunity in the area of local soap production using these ashes for self-reliance.

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ABSTRACT: In this paper, a new low power pulse-triggered Flip-Flop is designed with enhanced latch where the pulse-generation circuit is constructed using one pmos transistor and Data is transferred through two nmos transistors and a inverter, when compared with the conventional pulse-triggered flip-flops, it consumes only 0.373μw of power to activate the circuit and occupies only less area on chip i.e. 5 transistors and two inverters. The simulation results are done based on CMOS 50 nm technology.

Keywords: Flip-Flop, Low power, Pulse-triggered

[1] Yin-Tsung Hwang, Jin-Fa Lin, and Ming-HwaSheu "Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme" in IEEE Transactions on (vlsi) systems, vol. 20, no. 2, february 2012.

[2] A. G. M. Strollo, D. De Caro, E. Napoli, and N. Petra, "A novel highspeed sense-amplifier-based flip-flop,"IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 11, pp. 1266–1274, Nov. 2005.

[3] S. D. Naffziger, G. Colon-Bonet, T. Fischer, R. Riedlinger, T. J.Sullivan, and T. Grutkowski, "The implementation of the Itanium 2microprocessor,"IEEE J. Solid-State Circuits, vol. 37, no. 11, pp.1448–1460, Nov. 2002.

[4] J. Tschanz, S. Narendra, Z. Chen, S. Borkar, M. Sachdev, and V. De,"Comparative delay and energy of single edge-triggered and dual edge triggered pulsed flip-flops for high-performance microprocessors," inProc. ISPLED, 2001, pp. 207–212.

[5] F. Klass, C. Amir, A. Das, K. Aingaran, C. Truong, R. Wang, A. Mehta,R. Heald, and G. Yee, "A new family of semi-dynamic and dynamic flipflops with embedded logic for high-performance processors,"IEEEJ.Solid-State Circuits, vol. 34, no. 5, pp. 712–716, May 1999.

[6] H. Kawaguchi and T. Sakurai, "A reduced clock-swing flip-flop (RCSFF) for 63% power reduction,"IEEE J. Solid-State Circuits, vol.33, no. 5, pp. 807–811, May 1998.

[7] H. Partovi, R. Burd, U. Salim, F. Weber, L. DiGregorio, and D. Draper,"Flow-through latch and edge-triggered flip-flop hybrid elements," in IEEE Tech. Dig. ISSCC, 1996, pp. 138–139.

ABSTRACT: The Fast Fourier Transform (FFT) is a capable algorithm to compute the Discrete Fourier Transform (DFT) and it's inverse. It has a number of applications in the field of signal processing. The usual butterfly FFT design requires needless computations and data storage which lead to unnecessary power consumption. Use of the IEEE-754 standard 32-bit floating-point format also facilitates using the Fast Fourier Transform (FFT) processors. This paper describes two fused floating-point operations and applies them to the implementation of Fast Fourier Transform (FFT) processors using VHDL. The fused operations are a two-term dot product and add-subtract unit. The FFT processors use "butterfly" operations that consist of multiplications, additions, and subtractions of complex valued data. The statistical results of the fused implementations are slightly more accurate.

Keywords: Fast Fourier Transform (FFT), Floating-Point, Radix-2 Butterfly, VHDL.

[1] Earl E. Swartzlander Jr., and Hani H.M. Saleh, "FFT Implementation with Fused Floating-Point Operations," in IEEE Transactions on Computers, 2012.
[2] IEEE Standard for Floating-Point Arithmetic, ANSI/IEEE Standard 754-2008, Aug. 2008.
[3] Sneha N.kherde and Meghana Hasamnis, "Efficient Design and Implementation of FFT," in International Journal of Engineering Science and Technology, 2011.
[4] H.H. Saleh and E.E. Swartzlander, Jr., "A Floating-Point Fused Dot-Product Unit," Proc. IEEE Int'l Conf. Computer Design (ICCD), 2008.
[5] H.H. Saleh, "Fused Floating-Point Arithmetic for DSP," PhD dissertation, Univ. of Texas, 2008.
[6] H. Saleh and E.E. Swartzlander, Jr., "A Floating-Point Fused Add-Subtract Unit," Proc. IEEE Midwest Symp. Circuits and Systems (MWSCAS), pp. 519- 522, 2008.