Version-1 (May-June 2017)
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| Paper Type | : | Research Paper |
| Title | : | An Area Efficient FFT Structures Design by Sharing Arithmetic Units |
| Country | : | India |
| Authors | : | Pradnya Zode || Dr.A.Y.Deshmukh |
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: | 10.9790/4200-0703010107  |
ABSTRACT: Low power consumption has become apparent need in the area of VLSI digital signal processing. This gives rise to the need of minimization of silicon area which can be done by folding algorithm. As silicon area decreases power consumption of a circuit decreases. Folding transformation is a technique which reduces silicon chip area by combining various arithmetic operations into one operation by time scheduling technique. It is applied on iterative with appropriate folding set. This paper presents an approach to design fast Fourier transform (FFT) architectures using folding transformation...........
Keywords: Data flow graph, Fast Fourier transform, Folding transformation technique, Parallel-pipelined, Radix-3 algorithm.
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| Paper Type | : | Research Paper |
| Title | : | Design and Synthesis of Multiplexer based Universal Shift Register using Reversible Logic |
| Country | : | India |
| Authors | : | N. Srinivasa Rao || P.Satyanarayana |
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: | 10.9790/4200-0703010813 |
ABSTRACT: Reversible logic has shown wide applications in emerging technologies such as quantum computing, optical computing, and extremely low power VLSI circuits. Recently, many researchers have focused on the design and synthesis of efficient reversible logic circuits. In this work, as an example of reversible logic sequential circuits, we propose a novel reversible logic design of the Universal Shift Register. Here, we proposed a D-flip-flop whose efficiency is shown in terms of garbage output, constant input and number of reversible gates. Using this D flip-flop, efficient universal shift register is proposed. Universal shift register is a register that has both right and left shifts and parallel load capabilities. The proposed designs were functionally verified through simulations using Verilog Hardware Description Language.
Keywords: Reversible Logic, Reversible Gate, Shift Register
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