IOSR Journal of VLSI and Signal Processing (IOSR-JVSP)

Current Issue Vol2-Issue1

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Paper Type : Research Paper
Title : Performance Analysis of CMOS and FinFET Logic
Country : India
Authors : R.Rajprabu,V. Arun Raj, R. Rajnarayanan, S. Sadaiyandi, V. Sivakumar
: 10.9790/4200-0210106      logo

ABSTRACT: MOS is an old transistor technology that provides low power consumption, but has a shorter channel for the flow of current and thereby has some drawbacks like excessive current usage and larger size. The FinFET (Fin Field Effective Transistor) is an upcoming technology has a longer channel gate. The size ranges from 32nm, 22nm by Intel and finally it has been shrunk to 14nm by Samsung. This project is a study of these two technologies and we are able to distinguish the techniques and make CMOS as worth as FinFET.

Keywords : CMOS,FinFET,Samsung,Fin

[1] R. Chau, J. Kavalieros, B. Roberds, R. Schenker, D. Lionberger, D. Barlage, B. Doyle, R. Arghavani, A. Murthy, and G. Dewey, "30 nm physical gate length cmos transistors with 1.0 ps n-mos and 1.7 ps p-mos gate delays," in Electron Devices Meeting, 2000. IEDM'00. Technical Digest. International. 1em plus 0.5em minus 0.4em IEEE, 2000, pp. 45–48.
[2] T. Poiroux, M. Vinet, O. Faynot, J. Widiez, J. Lolivier, T. Ernst, B. Previtali, and S. Deleonibus, "Multiple gate devices: advantages and challenges," Microelectronic Engineering, vol. 80, pp. 378–385, 2005.
[3] F. Rossem, "Doping extraction in finfets," 2009.
[4] F. van Rossem, "Doping extraction in finfets," 2009.
[5] B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C.-Y. Yang, C. Tabery, C. Ho, Q. Xiang, T.-J. King et al., "Finfet scaling to 10 nm gate length," in Electron Devices Meeting, 2002. IEDM'02. International. 1em plus 0.5em minus 0.4em IEEE, 2002, pp. 251–254.


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Paper Type : Research Paper
Title : CHIPSCOPE Implementation of CRC circuit architecture
Country : India
Authors : G.Shanthi, Dr.L.Padmasree
: 10.9790/4200-0210714      logo

ABSTRACT: TCyclic Redundancy Check is an established technique for detecting errors on serial data communication links and in mass storage devices. A frame check sequence is appended to the message for transmission error detection in Many (high-speed) serial data communication protocols. The common hardware solution for CRC calculation is the linear feedback shift register (LFSR), consisting a few Flip Flops and Logic Gates. CRC is the preferred and most efficient method used for detecting bit errors produced from medium related noise. Data storage is another area where CRC error detection is becoming increasingly important. CRC checks to be executed at high speed as well as parallel processing. The ability of CRC implemented in hardware to be reconfigurable to handle new Generator polynomials will offer a key advantage in this fast developing area. The reconfigurable CRC circuit that has been implemented can quickly switch between any polynomial gives it a key advantage over the other circuits. In this paper it is proposed

Keywords - CRC (cyclic Redundancy check) ,FEC(Forward Error correction), Generator polynomial, LFSR(Linear feed back Shift Register), Reconfigurable circuit

[1] Data Communications and Networking , Third Edition By Behrouz A.Forouzan.

[2] P. Koopman and T. Charkravarty, "Cyclic Redundancy Code (CRC) polynomial selection for embedded networks," in Proc. DSN, pp. 145–154.

[3] Design and Implementation of a Field Programmable CRC Circuit Architecture, Ciaran Toal, Kieran cLaughlin, Sakir Sezer, and Xin Yang

[3] P. Koopman, "32-bit cyclic redundancy codes for internet applications," in Proc. DSN, pp. 459–472.640–651, Dec. 1995.

[5] T. Bi-Pei and C. Zukowski, "High-speed parallel CRC circuits in VLSI," IEEE Trans. Commun., vol. 40, no. 4, pp. 653–657, Apr. 1992.

[6] J. H. Derby, "High-speed CRC computation using state-space transformations," in Proc. Globecom, Nov. 2001, pp. 166–170.

[7] M.-D. Shieh, M.-H. Sheu, C.-H. Chen, and H.-F. Lo, "A systematic approach for parallel CRC computations," J. Inf. Sci. Eng., vol. 17, pp.445–461, 2001.

[8] T. Henriksson and D. Liu, "Implementation of fast CRC calculation," in Proc. ASP-DAC, 2003, pp. 563–564.

[9] F. Monteiro, A. Dandache, A. M‟sir, and B. Lepley, "A fast CRC implementation on FPGA using a pipelined architecture for the polynomial division," in Proc. ICECS, 2001, vol. 3, pp. 1231–1234.

[10] O. Weiss, M. Gansen, and T. Noll, "A flexible data path generator for physical oriented design," in Proc. ESSCIRC, Villach, Sep. 2001, pp. 408–411.


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Paper Type : Research Paper
Title : Improving Vmin of Sram by Schmitt-Trigger/Read-Write Techniques
Country : India
Authors : Surjith.N, Mrs. P.Arulmozhi, Dr.C.N.Marimuthu
: 10.9790/4200-0211520      logo

ABSTRACT: In modern Trends, the demand for memory has been increases tremendously. The reduction in SRAM operating voltage, cell stability and the increase in process variation with process scaling are the main concerns and can be done by Schmitt-Trigger Techniques. Read and write assist techniques are now commonly used to lower the minimum operating voltage (Vmin) of an SRAM. This paper presents a proposed 7T, 8T SRAM cell based on a various read and write assist technique and reduces the total power consumption and not area overhead of SRAMs while maintaining their performance and compare the output power. Simulation results with 180nm, 120nm CMOS technology.

Keywords - Low-Voltage SRAM, Process Tolerance, Schmitt-Trigger (ST), Vmin.

[1] Jaydeep P. Kulkarni. Kaushik Roy.: ―Ultralow-Voltage Process-Variation Tolerant Schmitt- Trigger-Based SRAM Design‖, IEEE Transaction on Very Large Scale Integration (VLSI) Systems, Vol.20, NO.2, Febraury 2012.

[2] K. Takeda, Y. Hagihara, Y. Aimoto, M. Nomura, Y. Nakazawa, T. Ishii, and H. Kobatake, ―A read-static-noise-margin-free SRAM cell for low-Vdd and high-speed applications,‖ in Proc. Int. Solid State Circuits Conf., Feb. 2005, pp. 478–479.

[3] N. Verma and A. P. Chandrakasan, ―65 nm 8T sub-Vt SRAM employing sense-amplifier redundancy,‖ in Proc. Int. Solid State Circuits Conf., Feb. 2007, pp. 328–329.

[4] V. Ramadurai, R. Joshi, and R. Kanj, ―A disturb decoupled column select 8T SRAM cell,‖ in Proc. Custom Integr. Circuits Conf., Sep. 2007, pp. 25–28.

[5] Y. Morita, H. Fujiwara, H. Noguchi, Y. Iguchi, K. Nii, H. Kawaguchi, and M. Yoshimoto, ―An area-conscious low-voltage-oriented 8T-SRAM design under DVS environment,‖ in Proc. VLSI Circuit Symp., Jun. 2007, pp. 14–16.

[6] M. Grossar, M. Stucchi, K. Maex and W. Dehaene, ―Read Stability and Write-ability analysis of SRAM Cells for Nanometer Technologies‖, IEEE J. Solid State Circuits, vol.41, no. 11, pp. 2577-2588, Nov. 2006.

[7] Z. Liu and V. Kursun, ―High read stability and low leakage cache memory cell,‖ IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 16, no. 4, pp. 488–492, Apr. 2008.

[8] S. Lin, Y.-B. Kim, and F. Lombardi, ―A highly-stable nanometer memory for low-power design,‖ in Proc. IEEE Int. Workshop Design Test of Nano Devices, Circuits Syst., 2008, pp. 17–20.

[9] J. P. Kulkarni, K. Kim, and K. Roy, ―A 160 mV robust Schmitt trigger based subthreshold SRAM,‖ IEEE J. Solid-State Circuits, vol. 42, no.10, pp. 2303–2313, Oct. 2007.

[10] J. P. Kulkarni, K. Kim, S. Park, and K. Roy, ―Process variation tolerant SRAM array for ultra low voltage applications,‖ in Proc. Design Autom. Conf. , Jun. 2008, pp. 108–113.


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Paper Type : Research Paper
Title : Detection of Faults in SRAM Using Transient Current Testing
Country : India
Authors : Anumol K A, N.M.Siva Mangai , P.Karthigaikumar, Minu E Mathew
: 10.9790/4200-0212126      logo

ABSTRACT:Fast development of memory devices cause more area occupation of memory in a chip and the strong market competition have increased the standards of the produced memories. The increased demand on reliability has, in turn, stressed the importance of failure analysis and device testing techniques. More and more effort and thought is being dedicated to the study of testing memory devices with regards to new fault models, fault diagnosis and new memory architectures. In order to detect these faults, March test has been widely used. However, some defects on SRAM cells may not be detected by the conventional March tests. This detection of defects in CMOS SRAM has been a time consuming process. Hence we go for current testing method. This paper implements a transient current testing (IDDT) method to detect defects in CMOS SRAM cells. By monitoring a transient current pulse during a transition write operation or a read operation, defects can be detected. In order to measure the transient current pulse, a current monitoring circuit is designed.

Keywords— SRAM, memory testing, March algorithm, IDDT, Current sensor circuit.

[1] Semiconductor Industry Association 2005 "International Technology Roadmap for Semiconductors ".
[2] Semiconductor Industry Association 2011 "International Technology Roadmap for Semiconductors".
[3] Van de Goor 1993, ―Using March Tests to test SRAMs,‖ IEEE Design and Test of Computers, March, pp. 8-14.
[4] Luigi Dilillo, Patrick Girard May 2004 ―Dynamic Read Destructive in Embedded-SRAMs: Analysis and March Test Solution‖ 9th IEEE European Test Symposium Congress Center, Ajaccio, Corsica, France
[5] Rubio, J. Figueras, J. Segura 1990, ―Quiescent current sensor circuits in digital VLSI CMOS testing‖, Electronic Letters, Vol. 26, pp. 1204-120. [6] Balachandran 1996, ―Improvement of SRAM-based failure analysis using calibrated Iddq testing‖ VLSI Test Symposium, Proceedings of 14th , IEEE pp. 130 – 136
[7] Sunil Jadav1, Vikrant2, Munish Vashisath June 2012 ―Design and performance analysis of ultra Low power 6t sram using adiabatic Technique‖ International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.3 [8] R. Rodriquez 2002, ―Resistance Characterization of Interconnect Weak and Strong Open Defects‖, IEEE Design & Test of Computers, vol.19, n.5, Sept-, pp.18-26
[9] Luigi Dilillo, Patrick Girard 2004 ―Resistive-Open Defects in Embedded-SRAM core cells: Analysis and March Test Solution‖ 13th Asian Test Symposium , Kenting, Taiwan Nov 15-17 [10] Fonseca 2010 ―Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes‖ Test Symposium (ETS), 15th IEEE European


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Paper Type : Research Paper
Title : Fractal Image Compression Based On Entropy Technique
Country : Iraq
Authors : JamilaH.Suad
: 10.9790/4200-0212730      logo

ABSTRACT: Our proposed approach presents a method to reduce the encoding time called Fast Algorithm of Fractal Image Compression based on Entropy Values (FAFICEVs). This technique will be reducing the size of the domain pool. FFICEVs technique is based on the observation that many blocks domain are never used in a typical fractal encoding, and only a fraction of this large domain pool is actually used in the fractal coding. The collection of used domain blocks is localized in regions with high degree of structure. This technique focuses on the implementation issues and presents the first empirical experiments analyzing the performance of benefits of entropy approach to fractal image compression. The experiment is carried out with technique of quadtree partitioning, allowing up to three (4x8, 4x16, and 8x16 pixel) is examined. The new algorithm gives a good quality of reconstructed image with speeding in encoding time.

Keywords: entropy, fractal encoding, image compression, partitioning, and quadtree.

[1] M. Barnsley and L. P. Hurd, Fractal Image Compression (AK Peters.Ltd, 1993).

[2] Fisher Y., Fractal Image Compression: Theory and Application (SpingerVerlag Edition, New York, 1995).

[3] Sofia Doudaet. al., A new approach for improvement of fractal image encoding ,International Journal on Computer Science and Engineering ,2(4),2010, 1387-1394.

[4] CorinaS_araru, Image Compression Based on Fractal Properties: Fractal Image Compression Optimization Methods, Nonlinear Phenomena in Complex Systems, 11 (2), 2008, 184 – 186.

[5]. Jamila H., Fractal Image compression, doctoral thesis, college of science, university of Baghdad,Iraq,2001.


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Paper Type : Research Paper
Title : Design of a Decimator Filter for Novel Sigma-Delta Modulator
Country : India
Authors : Kusum Lata, Manoj Duhan
: 10.9790/4200-0213137      logo

ABSTRACT: In this paper, the designing of decimation filter for sigma-delta (Σ-Δ) ADC having different oversampling ratio (OSR) is described. The decimation filter perform the operation of down sampling of a high frequency, low resolution signal to Nyquist rate, high resolution digital output. The design of a decimation filter is projected that employs IIR-FIR structure; second order Cascaded Integrator Comb (CIC) filters. This approach eliminates the need for multiplication, requires a maximum clock frequency equal to the sampling. Specifications of decimation filter are dependent upon the overall specification from Σ-Δ A/D converter with sampling frequency 5 MHz. The design implements a decimation ratio of 16, 64 allows a maximum resolution of 9,13 bits in the output of the filter respectively and implemented in 0.25μm CMOS technology. The overall objective is to optimize the decimator in terms of performance and reliability .This paper examines the practical design criteria for implementing the decimator in Σ-Δ ADC.

Keywords - cascaded integrator comb filter (CIC), IIR-FIR Structure, oversampling ratio (OSR), sigma-delta modulator, SPICE..

[1] Raghavendra Reddy Anantha, "A programmable CMOS decimator for sigma-delta ADC and charge pump circuits" , Louisiana State University, May 2005.

[2] Lucien Breems and Johan H. Huijsing, "Continuous Time Sigma Delta Modulation for A/DConversion in Radio Receivers", Kluwer Academic Press, 2001.

[3] Alexander Mora-Sanchez, Dietmar Schroeder, "Low-power decimation filter in a 0.35nm CMOS technology for a multichannel biomedical data acquisition chip", Proceedings of the XI IBERCHIP Workshop, p. 199-202 March 2005.

[4] Bibin John, Fabian Wagner and Wolfgang H. Krautschneider, "Comparison of Decimation Filter Architectures for a Sigma-Delta Analog to Digital Converter", Institute of Nanoelectronics Hamburg University of Technology (TUHH), 2005.

[5] G. Stephen, R. W. Stewart, "Sharpening of partially non-recursive CIC decimation filters," Asilomar Conference on Signals Systems and Computers, Vol. 2, pp. 2170-2173, November2004.


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Paper Type : Research Paper
Title : Ocean Ambient Noise and Its Directionality Measurement
Country : India
Authors : SivaKumar.V.G, Dr.V.Rajendran, Sailaja.M
: 10.9790/4200-0213844      logo

ABSTRACT: Sound is the effective way of communication underwater. It is the only radiation that can travel long ranges in water. Source, medium, detector (receiver) are three main elements for propagation. Ambient noise is the surrounding noise that is combined by different sources which impacts underwater sound communication and needs to be classified. Directionality attribute of the ambient noise are analyzed with respect to varying wind speeds, varying hydrophone depths and also for different frequencies. The ambient noise data are collected from the hydrophones placed at specific locations at Arabian Sea and Bay of Bengal. Low frequency noise arrives from the horizontal, as frequency increases, the vertical and near vertical contributions increase more rapidly than horizontal contributions. So vertical directionality is the key attribute of ambient noise to identify its source. In shallow water ambient noise and its vertical directionality are studied using vertical array of hydrophones. The properties of seabed vary spatially and thus provide an idea of site-specific characteristics. The channel and it boundaries specification are fetched by the noise propagating through the shallow water along its path of transmission. Hence the environment information can be detected from the noise properties.

Keywords - Ambient noise, vertical directionality, hydrophone depths..

[1] Douglas H. Cato, Ocean Ambient Noise: Its Measurement and Its Significance to Marine Animals, Defence Science and Technology Organisation, and University of Sydney Institute of Marine Science, Sydney, NSW 2006 Australia, Proceedings of the Institute of Acoustics.

[2] Editors: Mark Simmonds, Sarah Dolman and Lindy Weilgart, Oceans of Noise 2004, A WDCS Science Report, WDCS, the Whale and Dolphin Conservation Society, Brookfield House, 38 St Paul St, Chippenham, Wiltshire, SN15 1LJ, (chapter 2.1.1).

[3] R. J. URICK, Adjunct Professor, The Catholic University of America Washington, D.C. 20046 ,Published by undersea warfare published by Undersea warfare technology office naval sea systems command department of the navy Washington,D.C.20362.

[4] M. C. Sanjana and G. Latha, Member, IEEE, Peer-Reviewed Technical Communication, Midfrequency Ambient Noise Notch using Time-Series, Measurements in Bay of Bengal, IEEE Journal of Oceanic Engineering, VOL. 37, NO. 2, APRIL 2012 255.

[5] M. J. Buckingham and S. A. S. Jones, A new shallow ocean technique for determining the critical angle of the seabed from the vertical directionality of the ambient noise in the water column, J. Acoust. Soc. Amer., vol. 81, no. 4, pp. 938–946, 1987.

[6] C. H. Harrison and D. G. Simons, Geoacoustic inversion of ambient noise: A simple method, J. Acoust. Soc. Amer., vol. 112, no. 4, pp. 1377–1389, 2002.

[7], [8], (8) Allan G.Piersol, Time Delay Estimation Using Phase Data, IEEE Transactions on Acoustics, speech and signal processing..


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Paper Type : Research Paper
Title : Design of Low Power and High Speed CMOS Buffer Amplifier with Enhanced Deriving Capability
Country : India
Authors : Ajay Yadav, Shyam Akashe
: 10.9790/4200-0214550      logo

ABSTRACT: A high driving capability CMOS buffer amplifier with a novel concept of telescope-cascaded differential stages has been designed in present paper. The circuit describes here the capacitive load behaviour with reduced distortion at output node. A high slew rate of 36.54 v/μs is achieved with minimizing the quiescent current in the present circuit. A uniform voltage gain of 12.11 is obtained by varying the capacitive load [1nf to 5nf].The circuit has been fabricated using 180 nm technology. With 5nf load capacitor is efficiently used for charging capability in a ±1.8 v power supply. In a designed circuit, we attained overall power consumption 70.5 μW and improved tranconductance 3.561μs/μm.

Keywords - Buffer amplifier, slew rate, cascaded stages, source driver.

[1.] S.K. Kim, Y.-S. Son, and G.H. Cho, ―Low-power high-slew-rate CMOS buffer amplifier for flat panel display drivers,‖ Electron. Let., vol. 42, no4, 2006, pp. 4, 2006,pp. 214-215.

[2.] J.M. Carrillo, R.G. Carvajal, A. TorrUUlba, and J.F. Duque-Carrillo, ―Rail-to-rail low-power high-slew-rate CMOS analogue buffer, Electron. Lett., vol. 40, no. 14, 2004, pp. 214-215

[3.] P.-C. Yu and J.-C. Wu, ―A class-B output buffer for flat-panel-display Column driver,"IEEE J. Solid-State Circuits, vol. 34, no. 1, 1999, pp. 116–119

[4.] C.-W. Lu, ―High-speed driving scheme and compact high-speed Low-power rail-to-rail class-B buffer amplifier for LCD applications,‖ IEEE J. of Solid-State Circuits, vol. 39, no. 11, 2004, pp. 1938-1947.

[5.] C.-W. Lu and K.-J. Hsu, ―A high-speed low-power rail-to-rail column driver for AMLCD application,‖ IEEE J. of Solid-State Circuits, vol. 39,no. 9, 2004, pp. 1313-1320.

[6.] R. L. Shuler and R. S. Askew, ―Low offset rail-to-rail operational Amplifier,‖ United States Application 20060097791, 2006

[7.] K. E. Brehmer and J. B. Wieser, ―Large swing CMOS power amplifier,‖ IEEE J. Solid-State Circuits, vol. SC-18, pp. 624-629, Dec.1983.

[8.] B, K. Abuja, W. M. Baxter, and P. R. Gray, ―A programmable CMOS dual channel interface processor,‖ in Dig, Tech, Pap. Int. Solid-State Circuits Conf., Feb. 1984, pp. 232-233

[9.] G. A. Rincon-Mora and P. E. Allen, ―A low-voltage, low quiescent current Low drop-out regulator,‖ IEEE J. Solid-State Circuits, vol. 33, no 1, pp. 36–44, Jan. 1998.

[10.] S. K. Lau, K. N. Leung, and P. K. T. Mok, ―Analysis of low-dropout Regulator topologies for low-voltage regulation,‖ in Proc. IEEE Conf. Electron Devices and Solid-State Circuits, Hong Kong, Dec. 2003, pp.379–382.[


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Paper Type : Research Paper
Title : Analysis and optimization of Active Power and Delay of 10T Full Adder using Power Gating Technique at 45 nm Technology
Country : India
Authors : Raju Gupta, Satya Prakash Pandey, Shyam Akashe, Abhay Vidyarthi
: 10.9790/4200-0215157      logo

ABSTRACT: An overview of performance analysis and comparison between various parameters of a low power high speed 10T full adder has been presented here. This paper shows comparative study of advancement over active power, leakage current and delay with power supply of (0.7v) .We have achieved reduction in active power consumption of 39.20 nW and propagation delay of 10.51 ns, which makes this circuit highly energy efficient and optimization can be achieved between power and delay. In this circuit we have reduced leakage current of 18.21 nA for power supply of 0.5v to 0.9v. Signification of these designs is substance by the simulation results obtained from cadence virtuoso tool at different technologies.

Keywords - Full Adder, Leakage Power, CMOS Circuit, Sleep Transistor.

[1] R. Shalem, E. John and L. K. John.A Novel Low Power Energy Recovery Full Adder CellProceedings of the IEEE Great Lakes Symposium of VLSI February 1999, pp. 380-383.

[2] A. P. Chandrakasan, S. Sheng and R. W. Brodersen.Low-Power CMOS Digital Design IEEE Journal of Solid State Circuits Vol. 27, No. 4, pp. 473-483.

[3] R. Pedram and M. Pedram."Low power design methodologiesKluwer Academic" Publisher, 1996.

[4] T. Callaway and E. Swartzlander, Jr., "Low power arithmetic components," inLow Power Design Methodologies. Norwell, MA: Kluwer, 1996, pp. 161–201.

[5] A. Shams, T. Darwish, and M. Bayoumi, "Performance analysis of low power 1-bit CMOS full adder cells," IEEE Trans. Very Large Scale Integr.(VLSI) Syst., vol. 10, no. 1, pp. 20–29, Feb. 2005.

[6] A. Shams and M. Bayoumi, "Performance evaluation of 1-bit CMOS adder cells," in Proc. IEEE Int. Symp. Circuit and Systems, Jul. 1999, pp. 27– 30.

[7] A.M. Shams, M.A. Bayoumi, "A novel high-performance CMOS 1-bit full-adder cell," IEEE Transactions of Circuits & Systems. II, Vol. 47, pp. 478–481, May 2000.

[8] N. Zhuang, H. Ho, "A new design of the CMOS full adder," IEEE. J. of Solid-State Circuits, Vol. 27, No. 5, pp. 840- 844, May 1992.

[9] Analysis and Comparison on Full Adder Block in Submicron Technology Massimo Alioto, Member, IEEE, and Gaetano Palumbo, Senior Member, IEEE 4 Delay Uncertainty Due to Supply Variations in Static and Dynamic Full Adders.

[10] G.Brindha,S.Deepa, " Design Of Multiplier Using 10T Full Adder" ISSN NO: 6602 3127 www.ijart.org Page | 45.


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Paper Type : Research Paper
Title : RTL Implementation of Viterbi Decoder using VHDL
Country : India
Authors : Hiral Pujara, Pankaj Prajapati
: 10.9790/4200-0216571      logo

ABSTRACT: Forward Error Correction techniques are utilized for correction of errors at the receiver end. Convolutional encoding is an FEC technique that is particularly suited to a channel in which the transmitted signal is corrupted mainly by additive white Gaussian noise (AWGN). Viterbi algorithm is a well known Maximum-likelihood algorithm for decoding of Convolutional codes. They have rather good correcting capability and perform well even on very noisy channels. It has been widely deployed in many wireless communication systems to improve the limited capacity of the communication channels. The main Objective of this paper is to describe comparative analysis between various FPGA Devices for proposed design resource optimized implementation of Viterbi Decoder. The base of comparison is simulation and synthesized result. In this paper, resource optimized Viterbi Decoder has been designed using Trace back architecture. The proposed Viterbi Decoder with rate ½ and constraint Length 3 has been designed using VHDL, simulated using Xilinx ISE Simulator and synthesized with Xilinx Synthesis Tool (XST). The Viterbi Decoder is compatible with many common standards, such as DVB, 3GPP2, 3GPP, IEEE 802.16 and LTE.

Keywords - Convolutional Encoder, Forward Error Correction (FEC), Traceback method, Viterbi Algorithm, Viterbi Decoder

[1] Mahe Jabeen and Salma Khan, Design of Convolution Encoder and Reconfigurable Viterbi Decoder, International Journal of Engineering and Science, Vol. 1, No.3, Sep 2012.

[2] P. Subhashini, D. R. Mahesh Varma and Y. David Solomon Raju, Implementation Analysis of adaptive Viterbi Decoder for High Speed Applications, International Journal of Computer Applications (0975-– 8887), Volume 31– No.2, October 2011

[3] S.V.Viraktamath and G.V.Attimarad, Impact of constraint length on performance of Convolutional Codec in AWGN channel for image application, International Journal of Engineering Science and Technology, Vol. 2(9), 2010, 4696-4700.

[4] Bernard Sklar, Digital Communications Fundamentals and Application, Published by Pearson education, Year 2003 [5] B.P.Lathi, Modern Digital and Analog Communication Systems, Third Edition.

[6] J.G. Proakis, Digital Communications, McGraw Hill.

[7] J. Bhaskar, A VHDL Primer, Third Edition

[8] Volnei A. Pedroni, Circuit Design with VHDL

[9] Christian Baumann, ―Field Programmable Gate Arrray (FPGA), Summary paper for the seminar Embedded System Architecture, University of Innsbruck, January 13, 2010.

[10] Matthias Kamuf, Member, IEEE, Viktor Öwall, Member, IEEE, and John B. Anderson, Fellow, IEEE, Optimization and Implementation of a Viterbi Decoder under Flexibility Constraints, IEEE Transactions on Circuits and Systems—I: Regular Papers,Vol. 55, No. 8, September 2008.