IOSR Journal of VLSI and Signal Processing (IOSR-JVSP)

Nov.-Dec. 2017 Vol 7 - Issue 6

Version 1

Paper Type : Research Paper
Title : Automatic Detection of Cardiac Arrhythmia through ECG Signal Analysis: A Review
Country : India
Authors : Gopisetty Ramesh || D. Satyanarayana || M. Sailaja
: 10.9790/4200-0706010112     logo

ABSTRACT: Analyzing the characteristics of an ECG signal plays a vital role in the detection of various Cardiovascular Diseases (CVDs). However the analysis of ECG signal is not a simple task. In this paper a broad survey is carried out over various approaches focused to analyze the characteristics of ECG signal to perform automatic Cardiac Arrhythmia detection. Initially, the details of ECG acquisition, Characteristics of ECG and the possible arrhythmias based on the abnormalities in the ECG signal are discussed. Based on the step by step execution of the system model, all the approaches are classified as preprocessing approaches, feature extraction approaches and classification approaches..........

Keywords: ECG, Cardiovascular Diseases, Cardiac Arrhythmia, Feature Extraction, MIT-BIH.

[1]. Harikrishnan S, Leeder S, Huffman M, Jeemon P, Prabhakaran D, A Race against Time: The Challenge of Cardiovascular Disease in Developing Economies. 2nd ed. New Delhi, India: New Delhi Centre for Chronic Disease Control; 2014.
[2]. Xavier D, Pais P, Devereaux PJ, Xie C, Prabhakaran D, Reddy KS, Gupta R, Joshi P, Kerkar P, Thanikachalam S, Haridas KK, Jaison TM, Naik S, Maity AK, Yusuf S; CREATE registry investigators. Treatment and outcomes of acute coronary syndromes in India (CREATE): a prospective analysis of registry data. Lancet., 371, 2008, pp: 1435–1442.
[3]. A.S. Adabag, G. Peterson, F.S. Apple, J. Titus, R. King, R.V. Luepker, "Etiology of sudden death in the community: results of anatomic, metabolic, and genetic evaluation", Am. Heart. J. 159, 2010, pp: 33–39.
[4]. J.J. Goldberger, A.E. Buxton, M. Cain, O. Costantini, D.V. Exner, B.P. Knight, D.Lloyd-Jones, A.H. Kadish, B. Lee, A. Moss, R. Myerburg, J. Olgin, R. Passman, D.Rosenbaum, W. Stevenson, W. Zareba, D.P. Zipes, "Risk stratification for arrhythmic sudden cardiac death: identifying the roadblocks", Circulation, 123, 2011, pp: 2423–2430.
[5]. M. Velic, I. Padavic, S. Car, "Computer aided ECG Analysis – State of the Art and Upcoming Challenges", 2013,.


Paper Type : Research Paper
Title : VLSI Implementation of Daubechies Wavelet Filter for Image Compression
Country : India
Authors : Aparna Lahane || Dr.V.B.Malode
: 10.9790/4200-0706011317     logo

ABSTRACT: To analyze the performance of orthogonal wavelet filters for image compression on variety of test images. The test images are of different size and resolution. The compression performance is measured, objectively peak signal to noise ratio and subjectively visual quality of image and it is found that orthogonal wavelets outperform. Under normal conditions, the DWT provides near perfect performance, but in situations requiring the transmission of images across noisy or bandwidth-limited channels, the performance of the wavelet algorithm may be improved by redefining the wavelet filter using an optimization algorithm. The discrete wavelet transform has a huge number of applications in science, engineering, mathematics and computer science. In numerical........

Keywords: Daubechies filter, DWT, MSC, PSNR, Compression Ratio

[1]. Chieh-chi kao, Jui-hsinlai, "VLSI architecture design of guided filter for 30 frames/s FULL-HD video", IEEE transactions oncircuits and systems for video technology, vol. 24, no. 3,March 2014, pp.513- 524 .
[2]. Kaiming He, Jian Sun, "Guided Image Filtering", IEEE Transactions On Pattern Analysis and Machine Intelligence, vol. 35, no. 6,,June2013,pp.1397-1409.
[3]. K. Wahid, V. Dimitrov, and G. Jullien, "VLSI architectures ofDaubechies wavelets for algebraic integers," J. Circuits Syst. Comput.,vol. 13, no. 6, pp. 1251–1270, 2004.
[4]. K. A. Wahid, V. S. Dimitrov, G. A. Jullien, and W. Badawy, "An algebraicinteger based encoding scheme for implementingDaubechiesdiscrete wavelet transforms," in Proc. Asilomar Conf. Signals, Syst.Comp., 2002, vol. 1, pp. 967–971


Paper Type : Research Paper
Title : New Techniques Used for Image Enhancement
Country : India
Authors : Imtiyaz Ahmad Reshi
: 10.9790/4200-0706011822     logo

ABSTRACT: Principle objective of Image enhancement is to process an image so that result is more suitable than original image for specific application. Digital image enhancement techniques provide a multitude of choices for improving the visual quality of images. Appropriate choice of such techniques is greatly influenced by the imaging modality, task at hand and viewing conditions. The paper focuses on techniques for image enhancement..

Keywords: Digital, Image Processing, Image Enhancement

[1]. Bhabatosh Chanda and Dwijest Dutta Majumder, 2012, Digital Image Processing and Analysis.

[2]. R.W.Jr. Weeks,(2012). Fundamental of Electronic Image Processing . Bellingham: SPIE Press

[3]. A. K. Jain, Fundamentals of Digital Image Processing. Englewood Cliffs, NJ: Prentice Hall, 2013.

[4]. R.M. Haralick, and L.G. Shapiro, Computer and Robot Vision, Vol-1, Addison Wesley, Reading, MA, 2012.

[5]. R. Jain, R. Kasturi and B.G. Schunck, Machine Vision, McGraw-Hill International Edition, 1995


Paper Type : Research Paper
Title : Process-Simulation-Flow And Metrology of VLSI Layout Fine-Features
Country : Greece
Authors : George P. Patsis
: 10.9790/4200-0706012328     logo

ABSTRACT: Increasing complexity of VLSI designs makes it hard to follow fine details within a large design. Especially in variability studies it is important to be able to determine for example, edge lengths in the x and y direction of mask shapes, within a device or a circuit. The line-edge roughness variation vs. length scales within the circuit is valuable information for the effects of variability of circuit performance. In the current article a simulation flow is presented to help circuit designer, gain more understanding of the fabricated features of their circuits. Is starts from mask files in CIF format and decomposes them into their corresponding layers in order to be used in electron-beam-lithography simulations, stochastic-lithography simulation and line width roughness metrology studies. The code is integrated in a complete software suite.

Keywords: Matlab, VLSI, layout, CIF, electron-beam lithography, stochastic-lithography, roughness, metrology.

[1]. https://en.wikipedia.org/wiki/Common_Intermediate_Format
[2]. G.P. Patsis, Ν. Glezos, Electron-beam lithography simulation for EUV mask applications, Journal of Physics: Conference Series, 10
(1), 2005, 385-388.
[3]. G. P. Patsis, N. Tsikrikas, I. Raptis, N. Glezos, Electron-beam lithography simulation for the fabrication of EUV masks,
Microelectronic Engineering, 83 (4-9 SPEC. ISS.), 2006, 1148-1151.
[4]. G. P. Patsis, M. D. Nijkerk, L. H. A. Leunissen, E. Gogolides, Simultation of material and processing effects on photoresist lineedge
roughness, International Journal of Computational Science and Engineering, 2 (3-4), 2006, 134-143.
[5]. G. P. Patsis, V. Constantoudis, A. Tserepi, E. Gogolides, Quantification of line-edge roughness of photoresists. I. A comparison
between off-line and on-line analysis of top-down scanning electron microscopy images, Journal of Vacuum Science and
Technology B: Microelectronics and Nanometer Structures, 21 (3), 2003, 1008-1018.


Paper Type : Research Paper
Title : VHDL-AMS Macro models of MOSFET. Consideration of Gate Length Variability And Single-Electron-Transistors
Country : Greece
Authors : George P. Patsis
: 10.9790/4200-0706012933     logo

ABSTRACT: The integrated circuit/system designers are faced with problems that involves nano-scale devices with far less than ideal characteristics, very high integration densities (i.e. giga-scale complexity), very high operation speeds and data transmission rates, and system-level integration of analog and digital functions. The single-electron tunnelling (SET) devices might be scaled down almost to the molecular level. Gate length variability due to intra or inter die variations can lead to considerable mismatch between devices even inside the same chip. This variability has to be considered in detail and new device models should be developed, aiming in modelling its effects on the electrical characteristics of the devices. In the current article, a simple mosfet model is extended to incorporate gate length variability. The model is coded in VHDL-AMS in order to be used for simulation of circuit behavior........

Keywords: mosfet, line-width-roughness, vhdl-ams, digital-gates, single-electron-transistor, coulombblockage, compact-device-modelling

[1]. Y. S. Yu, H. S. Lee, and S. W. Hwang, SPICE Macro-Modelling for the Compact Simulation of Single Electron Circuits, J.
Korean Phys. Soc. 33, 1998, 269.
[2]. G. P. Patsis, Modelling MOSFET gate length variability for future technology node, Phys. Stat. Sol. (a) 205 (11), 2008, 2541-2543.
Ansys site: http://www.ansys.com/


Paper Type : Research Paper
Title : Bathymetry Data Processing using Adaptive Filtering and Validation on Indian Reservoirs
Country : India
Authors : M Selva Balan || C R S Kumar
: 10.9790/4200-0706013440     logo

ABSTRACT: Reservoirs are the lifeline of India and it economy depends on irrigation and agriculture. Sedimentation process erodes the agricultural land as well as fills the storage capacity of the reservoirs. Proper estimation of the reservoir capacity depends on the accuracy of depth measurement which depends on the echo sounder output. However most of the data collected from Indian lake are affected by various noises due to submerged vegetation, nature of sediment, under water and mechanical noises. This paper analyses the depth data collected at two different lakesusing adaptive filters and geo statistical interpolation techniques. The objective is to evaluate most accurate volume.......

Keywords: Adaptive filtering, Bathymetry data, Data Interpolation, Sedimentation.

[1] W. Fernandes and B. Chakraborty, "Bathymetric Techniques and Indian Ocean Applications," Intech:Europe, pp. 1-29, 2012.

[2] "Hydrographic Survey of Lower Lake at Kateri belongs to Cordite Factory, Aruvankadu, using Single Beam Echo Sounder, Real Time Kinematic (RTK) DGPS technique, and Total Station. No:5399," CWPRS, PUNE, June 2016.

[3] P. Kokaje, R. Kawitkar and M. Balan, "Sediment classification technique using Single Beam Echo Sounder," International Journal of Advanced Research in Electrical, Electronics and Instrumentaion Engineering., vol. 4, no. 8, August 2015.

[4] J. Smith and B. Friedlander, "Adaptive multipath delay estimation," IEEE transactions on acoustics, speech, and signal processing, vol. 33, no. 4, pp. 812-822, 1985.

[5] A. Jarrot, C. Ioana and A. Quinquis, "Denoising underwater signals propagating through multi-path channels," in Europe Oceans, IEEE, 2005, pp. 501--506.


Paper Type : Research Paper
Title : Design of 45nm graded Strained Si-pMOSFET and comparative analysis for high performance VLSI circuit
Country : India
Authors : Pramod Martha || Ashish Tiwary || Kabiraj Sethi
: 10.9790/4200-0706014147     logo

ABSTRACT: Strain engineering has been emerged as a perfect solution for the short channel effects (SCE) such as hot electron effect and self-heating effect occurs in the device with Nano dimensions. In this work a 45nm Strained Si-PMOSFET designed and simulated in 2D ATLAS simulator. Due to strain effect the drain current observed is twice that of the Si control PMOS, also there is a decrement in threshold voltage(-0.9V).The transconductance is of 90 mS/mm. The proposed device also investigated also on the basis of the total current density and the electric field, and by comparison with conventional PMOS strained Si PMOS is suitable for modern ULSI circuits..

Keywords: Strain, graded junction, DIBL ,total current density

[1]. M.V Fischetti, S.E Laux, "Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys"Journal of Applied Physics, Vol .80,Issue. 4 pp.2234- 2252,1996
[2]. J. Welser, J. L. Hoyt, andJ. F. Gibbons, "Electron Mobility Enhancement in Strained-Si N-Type Metal-Oxide-Semiconductor Field-Effect Transistors", IEEE Electron Device Letters, vol. 15, no. 3, March 1994.
[3]. Athena User's manual, Silvaco Inc. 2005.
[4]. K. Rim, J. Welser*, J.L. Hoyt, and J.F. Gibbons," Enhanced Hole Mobilities in Surface-channel Strained-Si p-MOSFETs",IEDM,pp.517-519,1995.
[5]. Atlas User's manual, Silvaco Inc. 2013..



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