IOSR Journal of VLSI and Signal Processing (IOSR-JVSP)

Mar. - Apr. 2016 Vol 6 - Issue 2

Version 1

Paper Type : Research Paper
Title : Efficient Security for Data Transmission Using CDF-5/3 Lift-DWT and LSB Technique
Country : India
Authors : Mamtha Mohan || B.K.Sujatha

ABSTRACT: Stegnography hides the message information inside a specific digital media. In this paper we propose image steganography using CDF-5/3 lift-DWT and Least Significant Bit (LSB) technique. First CDF-5/3 lift-DWT is applied to cover image to generate LL, LH, HL and HH sub-bands. The message information is converted into corresponding ASCII code simultaneously. This code is embedded onto the LL band co-efficients of cover image whose positions are derived from shared key and perform inverse DWT to get stegano image which increase the security of message without degrading the quality of cover image.

Keywords: Discrete Wavelet Transform, Image Hiding, LSB Technique and Stegnography.

[1] Behrouz A. Forouzan, "Cryptography and Network Security", Tata McGraw-Hill, 2007.
[2] AnirbanGoswami, Dipankar Pal and NabinGhoshal, "Authentication Technique for Gray Images using DCT," Third International Conference on Emerging Applications of Information Technology, pp. 421 - 424, 2012.
[3] T Narasimmalou and Allen Joseph R, "Optimized Discrete Wavelet Transform based Steganography," IEEE International Conference on Advanced Communication Control and Computing Technologies, pp. 88 – 91, 2012.
[4] NedaRaftari and Amir MasoudEftekhariMoghadam, "Digital Image Steganography Based on Integer Wavelet Transform and Assignment Algorithm," Sixth Asia Modeling Symposium, pp. 87 – 92, 2012.
[5] SudhirKeshari and ShriGopalModani, "Weighted Fractional Fourier Transform based Image Steganography," International Conference on Recent Trends in Information Systems pp. 214 – 217, 2011.

Paper Type : Research Paper
Title : Designing A Tool Using GUI In MATLAB For Comparing Front- End Acoustic Features For Speaker Diarization System
Country : India
Authors : J. S. Sohal || Sukhvinder Kaur

ABSTRACT: This paper presents a Tool, designed in MATLAB mostly used to find and compare various types of features of speech signals which are used in Speaker Diarization system. It includes fundamental frequency, spectrogram, formant frequency, Mel Frequency Cepstral Coefficient (MFCC) and Vector Quantized-MFCC. Two applications for which the tool has been used are presented: one for recordings of single speaker and other for multiple speakers using single distant microphone (SDM). At the end, using cosine correlation method, various features are compared and found Modified MFCC is the best..

Keywords:Fundamental Frequency, Formant Frequency, MFCC, Spectrogram, Speaker Diarization

[1] X. Anguera, S. Bozonnet, N. Evans, C. Fredouille, G. Friedland, and O. Vinyals, "Speaker diarization : A review of recent research," IEEE Transactions on Audio, Speech and Language Processing., 20(2), February 2012, 356–370.
[2] M.T. Knox, N. Mirghafori, G. Friedland, "Exploring methods of improving accuracy for speaker diarization",in Interspeech Conf., Lyon, France, August 25-29, 2013, 2783-2787.
[3] S. Engelberg, Y. Saidoff, and Y. Israeli, "Voice identification through spectral analysis," IEEE Instrumentation and Measurement Magazine.October 2006, 52-55.
[4] Lee Chulhee, Hyun D., Choi Euisun, Lee Chungyong "Optimization Feature Extraction for Speech Recognition," IEEE Transactions on Speech and Audio Processing.11 (1), 2003, 80-87.
[5] Rabiner , L. and Schafer, R., Digital Processing of Speech Signals( Prentice Hall, Inc., Englewood Cliffs, New Jersey, 1978).

Paper Type : Research Paper
Title : Hardware Implementation of Canonic Signed Digit Recoding
Country : India
Authors : B.V.V.Kiran Kumar|| B.Kasi babu || M.Sri Vijay

ABSTRACT:This paper presents the implementation of convert a two's complement binary number into its canonic signed digit representation. In these CSD recoding circuits are functionally equivalent carriers H and K are described. They are computed in parallel reducing the critical path. They possess some properties that led to a simplification of the algebraic expressions minimizing the overall hardware implementation. When compared with other binary CSD with other architecture, new CSD recoding is more efficient. Power analysis and area estimation are performed for the designed CSDs.

Keywords: Canonic Signed Digit (CSD)

[1] I. Koren, Computer Arithmetic Algorithms (Second ed.), A.K. Peters, Ltd. (Ed.), 2002.
[2] B. Phillips, N. Burgess, Minimal weight digit set conversions, IEEE Transactions on Computers 53 (6) (2004) 666–677.
[3] K.Y. Khoo, A. Kwentus, A.N. Wilson, A programmable FIR digital filter using CSD coefficients, IEEE Journal of Solid-State
Circuits 31 (6) (June 1996) 869–874.
[4] J. Skaf, S.P. Boyd, Filter design with low complexity coefficients, IEEE Transactions on Signal Processing 56 (7) (2008) 3162–
[5] T. Williams, M. Ahmadi, W.C. Miller, Design of 2D FIR and IIR digital filters with canonical signed digit coefficients using
singular value decomposition and genetic algorithms, Circuits Systems Signal Processing 26 (1) (2007) 69–89.

Paper Type : Research Paper
Title : 32 Bit Floating Point Vedic Multiplier
Country : India
Authors : Swapnil Suresh Mohite || Sanket Sanjay Nimbalkar || Madhav Makarand Bhatkhande || Mrs. Rashmi Rahul Kulkarni

ABSTRACT: A conventional way of performing multiplication of two 32 bit floating point number can be replaced by using Vedic mathematics. Vedic mathematics is an ancient Indian system of mathematics which has a unique technique of calculation based on sixteen sutras. This 32bit floating point Vedic multiplier which use "urdhwa- triyagbhyam" sutra is analysed to be a more convenient and efficient method because it reduces the processing delay and saves time. We have written the required code in Vhdl Using Xilink Ise Series.

Keywords: Carry looks ahead adder, Floating point Multiplier, Single precision, Urdhwa-triyagbhyam, Vedic mathematics

[1]. Mr.S.S.Mohansundaram,A.Nirmalkumar,T.Arul Prakash "design of floating point multiplier using vedic mathematics" International journal of innovative science, engineering and technology, Vol 2 issue 1,January 2015

[2]. Pankaj Singh, Bhavinkakani "performance comparison of floating point multipliers by using different multiplication algorithm" International journal of electronics and communication, Vol.3 issue1,January 2015.
[3]. Ms. Rashmi Kulkarni ,"Comparison among different adders" ", International Organisation of science and research.Vol 5, Issue 6, 2015.
[4]. Yashkumar.M.Warkari, Prof.L.P.Thakre,Dr.A.Y.Deshmukh"Design of 6 bit vedic multiplier using vedic sutras" International journal of innovative science ,engineering and technology, Vol.3 issue 4,April 2014.
[5]. I.V.Vaibhav,K.V.Saicharan,V.Sravanthi, D. Shinivasulu "VHDL implementation of floating point multiplier using vedic mathematics".

Paper Type : Research Paper
Title : A Detection and Identification Method for Airtarget Acoustic Signal Characterization
Country : Egypt
Authors : Mazhar Taylel || Mahmoud Sabry

ABSTRACT: Detection and classification of Airtargets (ATs) commonly performed using radar. ATs become essential demand for detection and classification However; Acoustic signal application is one of the famous techniques that used to detect low flying ATs passively. Peak of Power Spectral Density (PSD) and corresponding frequency are considered as main features of ATs recognition. The represented method for ATs detection and classification using Discrete Cosine Transform (DCT) to extract ATs features.........

Keywords: Airtargets (ATs), discrete cosine transform (DCT), Standard Deviation, Power Spectral Density (PSD), Entropy, Euclidean distance.

[1]. Santosh K.Gaikwad, Bharti W.Gawali and Pravin Yannawar, A Review on Speech Recognition Technique, International Journal of Computer Applications (0975 – 8887) Volume 10– No.3, November 2010
[2]. Noelia Alcaraz Meseguer, Speech Analysis for Automatic Speech Recognition, Norwegian University of Science and Technology. Department of Electronics and Telecommunications. Master of Science in Electronics 2009
[3]. Aamir Mairaj, Detection and Identification of an Aircraft by Processing its Acoustic Signature, 2011 International Conference on Network and Electronics Engineering, IPCSIT, Singapore vol.11, 2011.
[4]. 0S. W. Rienstra and A. Hirschberg, An introduction to acoustics, Technische Universiteit Eindhoven, 1999.
[5]. Mei Jiansheng1, Li Sukang1 and Tan Xiaomei2, A Digital Watermarking Algorithm Based On DCT and DWT, International Symposium on Web Information Systems and Applications (WISA'09) Nanchang, P. R. China, May 22-24, 2009, pp. 104-107.

Paper Type : Research Paper
Title : Optimization of Floor-Planning Using Genetic Algorithm and Hybrid Partitioning Algorithm
Country : India
Authors : B.Mahalakshmi || CH.Sumalatha || G.Divya || G.Emilygrace

ABSTRACT: Floor-planning is one of the key design flow of VLSI chip designing process.Area miniaturization is the essence of compaction of any application circuit in chip designing. The physical design stages involve virtual design realizations iterated for their efficiency.For this purpose, the CAD algorithms offer avariety of solutions depending on the needs and specifications of the designer. The use of EDA tools help invisualization of the effects of design algorithms on the circuit performance and the dimensions of the floor areaoccupied by the design...........

Keywords: Floor-planning, CAD algorithms, EDA tools, genetic algorithm(GA), Hybrid Genetic Algorithm(HGA)

[1]. H. Murata, K. Fujiyoshi, S. Nakatake, and Y.Sajitani,"VLSI module placement based on rectangle-packing by thesequence-pair," IEEE Trans. on Computer Aided Design, vol. 15, pp. 1518-1524, Dec. 1996.
[2]. S.Nakatake, K.Fujiyoshi, H.Murata, and Y.Kajitani," Module Placement on BSG-Sructure and IC layoutApplicaios,"Proc.ICCAD,pp 484- 491,1996.
[3]. P.-N. Guo, C.-K. Cheng, and T. Yoshimura, "An O-Tree Representation of Non- Slicing Floorplan and ItsApplications,"Proc.DAC, pp. 268–273, 1999.
[4]. Y. C. Chang, Y. W. Chang, G. M. Wu, and S. W. Wu,"B*-Trees: A new representation for nonslicingfloorplans," DesignAutomation Conference, pp. 458-463. 2000
[5]. D.E. Goldberg, "Genetic Algorithms in Search, Optimization and Machine learning", Pearson Education, ISBN: 13: 9780201157673, 2004

Paper Type : Research Paper
Title : A Comparative Study of Various Methods for Underwater Image Enhancement and Restoration
Country : India
Authors : Alex Raj S.M. || Abhilash S. || Supriya M.H

ABSTRACT: Images taken underwater usually do not possess visual quality because of degradation in visibility. The propagated light from object to the camera undergoes attenuation and scattering before reaching the camera. Hence the images suffer from blurriness and lack of contrast. These effects which degrades the visibility of underwater images can be called as haze......

Keywords: Color correction, enhancement, haze, transmission map, underwater image

[1]. Y. Y. Schechner and N. Karpel, Recovery of Underwater Visibility and Structure by Polarization Analysis, IEEE Journal of Oceanic Engineering, 30(3), 2005, 570-587.
[2]. S. Bazeille, L. J. I. Quidu, and J. P. Malkasse, Automatic underwater image pre-processing, In Proc. of CMM, 2006.
[3]. K. Iqbal, R. Abdul Salam, A. Osman, and A. Zawawi Talib, Underwater image enhancement using an integrated color model, Int. J. Comput. Sci., 34(2), 2007, 2–12.
[4]. F. Petit, Anne-Sophie Capelle-Laizé and P. Carre, Underwater Image Enhancement by Attenuation Inversion with Quaternions, Proc. IEEE, 2009, 1177-1180.
[5]. K. Iqbal, M. Odetayo, A. James, R. A. Salam and A. Z. H. Talib, Enhancing the Low Quality Images using Unsupervised Colour Correction Method, In proc. IEEE International Conference on Systems Man and Cybernetics, 2010, 1703-1709

Paper Type : Research Paper
Title : Analytical and Comparative Study Of Quantum Dot Cellular Automata Technology Based 2:4 Decoder Circuits
Country : India
Authors : Manisha G. Waje || Dr. P. K. Dakhole

ABSTRACT: Quantum dot cellular Automata technology is used in this paper which overcomes the design constraints of nanoscale CMOS circuits. This paper presents the analysis of 2:4 decoder circuit using four different methodologies. QCA based Decoder circuit is implemented using coupled majority voter minority gate, 450 rotated cells, multilayer wire crossings and five input Majority Voter gate. Comparative study of these four decoder shows that performance of Coupled majority voter minority gate based 2:4 decoder is good in terms of area, latency and complexity. QCADesigner 2.0.3 tool is used for the implementation of QCA based Decoder circuits.
Keywords: Coupled majority voter minority gate, Decoder, Multilayer wire crossings, Quantum Dot Cellular Automata.

[1]. P. K. Bondy, "Moore‟s law governs the silicon revolution," Proceedings of the IEEE, vol. 88, no. 1, pp. 78-81, Aug. 2002.
[2]. International Technology Roadmap for Semiconductors, Process Integration Devices and Structures (PIDS),, 2011 Edition.
[3]. K. Walus, G.A. Jullien, Design tools for an emerging SoC technology: quantum-dot cellular automata. Proc. IEEE 94(6), 1225–1244 (2006
[4]. M Ozaki, Y. Adachi, Y. Iwahori, and N. Ishii, Application of fuzzy theory to writer recognition of Chinese characters, International Journal of Modelling and Simulation, 18(2), 1998, 112-116.
[5]. Rigui ZHOU, Xiaozhou ,"A Logic Circuit Design of 2-4 Decoder Using Quantum Cellular Automata", Journal of Computational Information Systems 8: 8 (2012) 3463–3469

Paper Type : Research Paper
Title : Comparative Analysis of Quaternary SETMOS Multiplexer
Country : India
Authors : Ms.Vaishali Raut || Dr.Pravin Dakhole

ABSTRACT: This paper introduces the comparative analysis of binary logic with quaternary logic.As quaternary logic build the circuits which are more compact and simple as compared with binary logic .For This two devices are used the first one is PMOS and other one is N-Type single electron transistor(NSET).For Comparative analysis basic hybrid SETMOS Quaternary logic gates as well binary SETMOS Quaternary logic gates are desined and simulated.Similarly three different multiplxers are designed and simulated .Comparison is done with the help of power dissipation.

Keywords: single electron transistor,mosfet,quaternary,binary power dissipation.

[1]. Hurst,S.L "Multiple-Valued Logic;its Status and its Future",Computers,IEEE Transactions on,33(12),pp.1160-1179, Dec. 1984.
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Paper Type : Research Paper
Title : Performance Evaluation of Gabor Wavelet Features for Face Representation and Recognition
Country : India
Authors : M. E. Ashalatha || Mallikarjun S. Holi

ABSTRACT: The choice of the object representation is crucial for an effective performance of cognitive tasks such as object recognition, fixation, etc. Face recognition is an example of advanced pattern recognition. The main aim is to investigate alternative methods to be used for face recognition, in particular the use of wavelets. The representation of images by Gabor wavelets is chosen for its biological relevance and technical properties. The Gabor wavelets are of similar shape as the receptive fields of simple cells in the primary visual cortex (V1)..............

Keywords: Face recognition, Feature extraction, Gabor wavelet, Sensitivity, Specificity.

[1] D. H. Hubel and T. N. Wiesel, "Receptive fields of single neurons in the cat‟s striate cortex", Journal of Physiology (1959) 148, pp.574-591.
[2] K P Soman, K L Ramachandran & N G Reshmi, "Insight into Wavelets from Theory to Practice", Third Edition, PHI Learning.
[3] Chun Lin, Liu, "A Tutorial of Wavelet Transform", Feb. 23, 2010.
[4] M Sifuzzaman, M R Islam and M Z Ali, "Applications of Wavelet Transform & its advantages compared to Fourier Transform", Journal of Physical Science, vol.13, 2009, pp.121-134.
[5] Michael Lyons, Shigeru Akamatsu, "Coding facial expressions with Gabor wavelets", Proceedings of Third IEEE International Conference on Automatic Face & Gesture Recognition, April 1998, Nara Japan, pp. 200-205.

Paper Type : Research Paper
Title : Low Power Design of Sr Flip Flop Using 45nm Technology
Country : India
Authors : Pratiksha Gupta || Dr. Rajesh Mehra

ABSTRACT: This paper illustrates the design of low-power, high-performance SR flip-flop. The speedy technical trends are engrossing to decrease the geometrical feature size and power consumption of the integrated circuit in VLSI designs. The proposed design shows the comparison with conventional CMOS circuit on the basis of power consumption and propagation delay and can save up to a significant amount of the power and speed..............

Keywords: VLSI design SR flip-flop, CMOS technology, power.

[1]. Yanun Dai; JizhongShen"An explicit-pulsed double edge triggered JK flip flop". IEEE Conference Publication,Volume-2 pp. 1-4, Year 2009.
[2]. Pinki& Rajesh Mehra, "Design of Low Power High Performance JK Flip Flop" International Journal of Scientific Research Engineering & Technology (IJSRE) ,14-15 ,March 2015.
[3]. Zhao Xianghong; GuoJiankang; Song Guanghui "An improved low power clock gating pulse triggered SR flip flop" .In IEEE International Conference on Networking and Automation, Volume – 2, pp.489-491, Year 2010.
[4]. Suresh Kumar.S "Sigh of Counter for low Power VLSI Circuit" In International Journal of Computer Science & Mobile Computing ,Volume-2, pp No.435-443,Year 2013

Paper Type : Research Paper
Title : Fused Floating Point Arithmetic Unit for Radix 2 FFT Implementation
Country : India
Authors : Prasanna Palsodkar || Ajay Gurjar

ABSTRACT: This paper describes the design and implementation of user defined fused floating-point arithmetic operations that can be used to implement Radix 2 butterfly Fast Fourier Transform (FFT) for complex numbers used in Digital Signal Processing (DSP- C) processors. This paper reports the comparison of area, delay and power of fused floating point modules as compared to discrete floating point with reference to Radix.............

Keywords: Floating point, DSP, Area, Power, Delay, FFT

[1]. E.E. Swartzlander, Jr. and H. H. Saleh, "FFT Implementation with Fused Floating-Point Operations," IEEE Transactions on Computers, , 61(2), 2012, 284-288.
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Transactions on circuits and systems-I, Vol. 59, no. Nov, 2012
[3]. H.Saleh and E.E. Swartzlander, Jr., "A Floating-Point Fused Add-Subtract Unit," Proc. IEEE Midwest Symp. Circuits and Systems (MWSCAS), pp. 519-522, Dec 2008.
[4]. IEEE Standard for Binary Floating-Point Arithmetic, ANSI/IEEE Standard 754-1985.
[5]. IEEE Standard for Floating-Point Arithmetic, ANSI/IEEE Standard 754-2008,Aug. 2008.

Paper Type : Research Paper
Title : Designing of Current-Mode Active Filter Using 45nm CMOS-Based CCII
Country : India
Authors : Jyoti Sharma || Saket Jhalani || Lakshya Dwivedi

ABSTRACT: Conventional design techniques in VLSI are in voltage mode but we experience various drawbacks like smaller bandwidth, low linearity, higher power consumption, less gain etc. Also, the power of any circuit is proportional to the product of the biasing voltage and biasing current and, if we concentrate on current signal rather than the voltage signal, a better control over power can be observed.............

Keywords: Active filter, Bandwidth, Cadence, CCII±, Current mirror, Current mode.

[1]. K. C. Smith and A. Sedra, A second generation Current Conveyor and its application,IEEE trans. Circuit theory, 17, 1970, 132-134.
[2]. K. C. Smith, 'the current conveyor: a new circuit building block, Proc. IEEE, 1968, 1368-1369
[3]. Allen, P.E. y D.R. Holberg, CMOS analog circuit design. New York (Oxford University Press, 2002).
[4]. J. Sharma and K. Shrama, 'Performance Evaluation of Electronic Tunable Filter Using CCCII 45nm CMOS Technology for WIFI Applications', International Journal of Science and Research, 5(3),2016,2053-2056
[5]. J. Sharma and A. Shrama, ' Universal Filter Design using 45nm CMOS-based DDCC for Bluetooth/Zigbee Application', International Journal of Computer Applications, 134(13),2016

Paper Type : Research Paper
Title : High Speed Level Shifter Design for Low Power Applications Using 45nm Technology
Country : India
Authors : Nisha || Rajesh Mehra

ABSTRACT: As the need of handheld devices such as cell phones, speakers, cameras etc., is growing, low power consumption has important design issues for integrated circuits. Level Shifter is an interfacing circuit which can interface low core voltage to high input- output voltage. In order to achieve reduction in power consumption and delay, the proposed level shifter named Single Supply Level Shifter (SSLS) has been designed ..............

Keywords: CMOS, Delay, Level shifter, Power consumption, Single supply level shifter.

[1]. Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa, "A Low-Power Level Shifter With Logic Error Correction for Extremely Low-Voltage Digital CMOS LSIs", IEEE Journal of Solid-State Circuits, Vol. 47, No. 7, July 2012, pp. 1776-1783.
[2]. Karthikeyan.G, Mathan.K, "Design and Analysis of Low Power Level Shifter", International Journal of Research in computer applications and Robotics (IJRCAR), Vol. 2, No. 12, Dec 2014, pp. 20-26.
[3]. Shilpa Thakur, Rajesh Mehra, "CMOS Design and Single Supply Level Shifter Using 90nm Technology", Conference on Advances in Communication and Control Systems, Vol. 8, No. 7, Dec 2013, pp. 150-153.
[4]. Devesh Dwivedi, Suman Dwivedi, Eswararao Potladhurthi, "Voltage up Level Shifter with Improved Performance and Reduced Power", IEEE Canadian Conference on Electrical and Computer Engineering (CCECE), Vol. 48, No. 6, Aug 2012, pp. 785-791.
[5]. S.Vaishnavi, S.Ashok, T.Mohammed Abbas, Arun Ragesh, Dr. Rangarajan, "Design and Analysis of Level Shifter in High Voltage Transmitter", International Journal of Scientific and Research Publications (IJSRP), Vol. 4, No. 1, Jan 2014, pp. 1-5.

Paper Type : Research Paper
Title : Studies on Watershed Segmentation for Blood Cell Images Using Different Distance Transforms
Country : India
Authors : CH. Nooka Raju || Dr.G.S.N. Raju || Dr.V.K. Varma Gottumukkala

ABSTRACT: In Biomedical images, image segmentation is a useful process. It partitions an image into its regions or objects. There are several complex images for which effective segmentation is one of the most difficult tasks in image processing. It is possible to use different useful algorithms for such purposes. It is well known that watershed segmentation is one of the most useful and important method for binary images.............

Keywords: Distance transform, Image, Segmentation, Watershed transform

[1]. Rafael C. Gonzalez and Richard E. Woods, Digital Image Processing (Prentice-Hall, 2002), 617-620.

[2]. Babak Yazdanpanah, G.S.N.Raju, K. Sravan Kumar , Reduction Noise of ECG Signal Using Extended Kalman Filter, International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE), 3(9), September 2014
[3]. Md. Shakoswat Zaman Sarker, Tan Wooi Haw and Rajasvaran Logeswaran, Morphological based technique for image segmentation, International Journal of Information Technology, 14( 1), 2007.
[4]. Manisha Bhagwat, R. K. Krishna and Vivek Pise, Simplified Watershed Transformation, International Journal of Computer Science and Communication, 1(1), 2010, 175-177.

Paper Type : Research Paper
Title : An Efficient Normalized Fractional LMS Algorithm Used To Enhance the Quality of ECG Signal
Country : India
Authors : Y. Karna Babu || T.Gowri

ABSTRACT: Adaptive filters are primary methods to remove the power line interference noise from the ECG signal. The frequency range of ECG signal is generally 0.05 Hz to 100 Hz, and that of the power line interference noise is 50 Hz which lies in the ECG signal. So, it has become very crucial to remove the power line interference from the ECG signal. In this paper Normalized fractional least mean square (NFLMS) algorithm had compared with others..............

Keywords: Power line interference; ECG signal; NFLMS; SNR

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[4]. Hsu-Chang., Huang, Junghsi Lee., 2011, A New Variable Step-Size NLMS Algorithm and Its Performance Analysis,IEEE Transactions On Signal Processing, Vol. 60, No. 4, April 2012,(1053-587x).
[5]. Hsu-Chang Huang and Jhunghsi Lee, A new variable step size NLMS Algorithm and its performance analysis, IEEE Transa.Signal Process., vol 60,no 4, pp.2055-2060,Apr 2012.

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