iosr-JVSP   Volume-6 ~ Issue-1 ~ Jan-Feb 2016

ABSTRACT: This paper discusses the design of picowatt power Sigma-delta modulator with genetic algorithm (GA) based oversampling technology. This Sigma-delta modulator design is paid special attention to its low power application of portable electronic system in digitizing biomedical signals such as Electro-cardiogram (ECG), Electroencephalogram (EEG) etc. [1]. A high performance, low power second order Sigma-delta modulator is more useful in analog signal acquisition system. Using Sigma-delta modulator can reduce the power consumption and cost in the whole system.

[1]. Joseph JC and John MB: Introduction to Biomedical Equipment Technology. In: Prentice Hall. Upper Saddle River, 2001.
[2]. Guessab S, Benabes P and Kielbasa R: A passive delta-sigma modulator for low-power applications. IEEE Circuits and Systems 2004; 3: 295-298
[3]. Leung SW and Zhang YT: Digitization of electrocardiogram (ECG) signals using delta-sigma modulation. IEEE Engineering in Medicine and Biology Society 1998; 4: 1964 -1966.
[4]. Samid L, Manoli Y: Micro Power Continuous-Time Sigma Delta Modulator. Conference on European Solid-State Circuits 2003; 165-168
[5]. Norsworthy SR, Schreier R, and Temes GC: Deltasigma converters: theory, design and simulation.In: IEEE Press, New York, 1997; 223-234.
[6]. Fujisaka H, Kurata R, Sakamoto M, Morisue M: Bit-stream signal processing and its application to communication systems. IEE Circuits, Devices and Systems 2002; 149: 159-166.

ABSTRACT: Different modalities can be achieved by the maximization of suitable statistical similarity measures within a given class of geometric transformations . The registration functions are less sensitive to low sampling resolution, do not contain incorrect global maxima which are sometimes found in the mutual information. This paper proposes a novel and straightforward multimodal image registration method based on mutual information, in which two matching criteria are used. It has been extensively shown that metrics based on the evaluation of mutual information are well suited for overcoming the difficulties of multi-modality registration.

Keywords: multimodalities, mutual information, metric

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[2] W. M. Wells III, P. Viola, H. Atsumi, S. Nakajima, and R. Kikinis, "Mult imodal volume regist rat ion by maximizat ion of mut ual
informat ion," Medical Image Analysis, vol. 1, no. 1, pp. 35–51, 1996.
[3] F. Maes, A. Collignon, D. Vandermeulen, G. Marchal, and P. Suet ens, "Mult imodalit y image regist rat ion by maximizat ion of
mut ual informat ion," IEEE Transact ions on Medical Imaging, vol. 16, no. 2, pp. 187–198,1997.
[4]. P . A. Van Den Elsen, E. J. D. Pol and M. A. Viergever, "Medical image mat ching: a review with classificat ion", IEEE Engineering
in medicine and biology, 12(1):1993,26-39

ABSTRACT: Dans cet article, nous allons accélérer l'algorithmed'indexation et de recherche d'images par le contenu basée sur la décomposition d'image en ses IMFs (fonctions modales intrinsèques) en utilisant les fonctions radiales de base à support compact (CSRBF) comme fonctions d'interpolation à la place des fonctions radiales de base globales.En général l'extraction de vecteur descripteurbasée sur la décomposition d'image en ses IMFss'appuie sur une corrélation spatiale des extrema de chaque IMF. L'efficacité de la méthode proposée est testée sur la base Columbia qui contient 1440 images décrivant 20 objets différents,constitués par des images avec différentes orientations et transformations d'échelle. Mots-clés: Recherche d'image, vecteur descripteur, BEMD, fonction CSRBF, corrélation spatiale

[1]. J.C. Nunes, Y. Bouaoune, E. Delechelle, O. Niang, Ph. Bunel. Image analysis by bidimensionalempirical mode decomposition. Image and Vision Computing Journal, 2003.
[2]. A. Sabri, Décomposition Multimodale Empirique Bidimensionnelle : Améliorations et Applications,doctorat national UFR : Automatique et analyse des systèmes, le 13 juin 2009.
[3]. ASabri, M. Karoud, M. Tairi, H. et A. Aarab. An efficient image retrievalapproachbased on spatial correlation of the extrema points of the IMFs. International Review on Computer and Software (I.RE.CO.S), ISSN: 1828- 6003, Vol.3 N.6, November 2008, P: 597-604
[4]. B S. Morse, T S. Yoo, P Rheingans, D T. Chen, K. R. Subramanian. Interpolating Implicit Surfaces From Scattered Surface Data Using Compactly Supported Radial Basis Function. Department of Computer Science, Brigham Young University, 2005.

ABSTRACT:Reversible logic has presented itself as a prominent technology which plays an imperative role in Quantum Computing. Quantum Computing devices theoretically operate at ultra high speed and consume infinitesimally less power. Research done in this paper aims to utilize the idea of reversible logic to break the conventional speed-power trade-off, thereby getting a step closer to realize Quantum computing devices. To authenticate this research, various combinational and sequential circuits are implemented such as a 4-bit
Ripple-carry Adder, (8- bit X 8-bit) Wallace Tree Multiplier, and the Control Unit of an 8-bit GCD processor using Reversible gates.

[1] Landauer, Rolf, "Irreversibility and heat generation in thecomputing process," IBM Journal of Research and Development ,vol.44,
no.1.2, pp.261,269, Jan. 2000doi: 10.1147/rd.441.0261
[2] Bennett, C.H., "Logical Reversibility of Computation," IBM Journalof Research and Development , vol.17, no.6, pp.525,532, Nov.
1973doi: 10.1147/rd.176.0525
[3] B, Raghu Kanth; B, Murali Krishna; G, Phani Kumar; J, Poornima,"A Comparative Study of Reversible Logic Gates",
InternationalJournal of VLSI & Signal Processing Applications, vol.2, Issue 1,Feb 2012, (51-55), ISSN 2231-3133 ( Online ).
[4] Morrison, M.; Ranganathan, N., "Design of a Reversible ALUBased on Novel Programmable Reversible Logic GateStructures,"
VLSI (ISVLSI), 2011 IEEE Computer Society AnnualSymposium on , vol., no., pp.126,131, 4-6 July 2011doi:
10.1109/ISVLSI.2011.30.
[5] Nachtigal, M.; Thapliyal, H.; Ranganathan, N., "Design of areversible single precision floating point multiplier based onoperand
decomposition," Nanotechnology (IEEE-NANO), 2010 10thIEEE Conference on , vol., no., pp.233,237, 17-20 Aug. 2010doi:
10.1109/NANO.2010.5697746 (Nachtigal, Thapliyal, &Ranganathan, 2010)

ABSTRACT:Paper discussed the comparative analysis ofdifferent full adder cells with two logic styles.The logic styles used for implementation of FinFET based 1-bit full adder are Complementary MOS (CMOS) and Transmission Gate (TG). The simulations of full adders have being done at 10nm, 20nm and 32nm technology node. PTM models for multi-gate transistors (PTM-MG) low power are used for simulations. This model is based on BSIM-CMG, a dedicated model for multi-gate devices. Investigation of performance and energy efficiency ofall types of full adder cell designs has been done. The performance metrics that were measured, analyzed and compared are average power, leakage power, delay, and energy. It is observed that less power is consumed in Transmission Gate (TG) based full adderthan the Convention full adder in 10nm technology node.

Keywords: FinFET, Full Adder, Logic Styles, HSPICE

[1]. A.Chandrakasan, W.Bowhill, and, F. Fox, ―Design of HighPerformance Microprocessor Circuits‖, IEEE Journal of Solid-State Circuits,Vo1.36, No.10, pp. 263 -271, Aug. 2001.
[2]. AnanthaChandrakasan, Robert W. Brodersen.,‖ Low Power CMOS Design‖IEEE Journal of Solid-State Circuits, New York,Vo1.36, No.8, pp. 1263 -1271, Aug. 1998
[3]. A. M. Shams, T. K. Darwish, andM.A. Bayoumi, ―Performance analysis of low-power 1-bit CMOS full adder cells,‖ IEEETransactions on Very Large Scale Integration (VLSI) Systems, vol. 10, no. 1, pp. 20–29, 2002.
[4]. http://ptm.asu.edu/modelcard/2006/32nm_bulk.pm
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[6]. http://ptm.asu.edu/modelcard/PTM-MG/modelfiles/lstp/10pfet.pm

ABSTRACT:The objective is to identify the status of the human behavior based on their facial expressions. A new idea for detecting human face as an input imagery and recognizing their facial expression using feature extraction parameters such as Angular second moment, Contrast and Homogeneity and behavior was achieved using Minimum distance classifier. A Facial Expression Recognition system needs to solve the following problems such as facial feature extraction and facial expression classification. The universally accepted seven principal emotions to be realized are Angry, Happy, Sad, Disgust, Fear and Surprise along neutral. The proposed method was evaluated on the JAFFE database images and Offline images using three of the facial expressions such as Happy, Sad and Neutral.

[1]. Nicu Sebe, Michael S, Lew, Ira Cohen, Ashutosh Garg, Thomas S.Huang, "Emotion recognition using a Cauchy naïve bayes
classifier", ICPR, 2002.
[2]. S. Gandhe, K. Talele, and A. Keskar, "Intelligent Face Recognition Techniques: A Comparative Study". GVIP Journal, Volume 7,
Issue 2, 2007.
[3]. S. Li, and J. Li, "Face Detection, Alignment, and Recognition". Emerging Topics in Computer Vision. Editors: G. Medioni, and S.
Kang. Chapter 9, pp 385-388, 2005 Person Education Inc.
[4]. Gaurav B. Vasani, Prof. R. S. Senjaliya, Prajesh V. Kathiriya, Alpesh J. Thesiya, Hardik H. Joshi, "Human Emotional State
Recognition Using Facial Expression Detection", International Journal Of Engineering And Science, 2013; 02 : 42-44.
[5]. P. Pavithra, A. Balaji Ganesh, "Detection of Human Facial Behavioral Expression Using Image Processing", ICTACT Journal on
Image and Video Processing, 2011; 01:162-165.

ABSTRACT:There has been requirement to evolve a general parallel architecture for concurrently processing Electrocardiogram(ECG) using Wavelet Transform based DSP algorithms. In order to acquire spatial ECG electrical signals, 12 ECG lead channels need to be digitized and concurrently processed by Wavelet Transforms, simultaneously acquiring from all the 12 leads. More over now a days 15 Channel ECG is also under consideration in research, for on-line monitoring of critical patient in an ICU situation, while asessing or monitoring load on heart, during treatment process. In these wavelet transform algorithms, matrix inverse operations using wavelet bases matrix, requring simultaneous matrix multiplications are involved.

[1]. R. B. Wallace, R.M. Dansereau, and R.A. Goubran, "Methods for the detection of ECG characteristic points",IEEE Symposium on
Medical Measurements and Applications Proceedings (MeMeA), 01/2012. Pp 1-6DOI: 10. 1109/MeMeA.2012.6226638
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n.2, 1992, pp.569-586
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pp. 76-79
[5]. H.A.N. Dinh, D.K. Kumar, N.D. Pah, P. Burton, Wavelets for QRS detection, Proceedings of the 23rd Annual International
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[6]. A. Cohen, J. Kovacevic, Wavelets: the mathematical background, Proceedings of the IEEE, Vol.84, 1996, pp.514-522
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of ECG Signal, Proceedings of the 27th Annual Conference of the IEEE Engineering inMedicine and Biology, Shanghai,
China, 2005, pp.1270-1273

ABSTRACT:A low cost design and simple to implement, CMOS NP Domino logic is presented. The NP Domino logic designs require fewer transistors and are compatible with full Domino logic. The performance of NP Domino logic is also better compared to the standard Domino logic implementations. Dynamic domino logic are very good but had many challenges like monotonicity, leakage, charge sharing and noise problems. These problems are totally eliminated in the CMOS NP Domino logic (which is also known as Zipper circuits) without any penalty in performance or silicon area utilization. This paper compares NP Domino logic with static CMOS and domino (dynamic) logic design implementations.

Keywords - CMOS, NP Domino logic, monotonicity, Zipper, static,

[1] Y. Berg an O. Mirmotahari: "Ultra Low-Voltage and High Speed Dynamic and Static Precharge logic", In Proc. of the 11 th Edition of IEEE Faible Tension Faible Consommation. June 6-8, 2012, Paris, France.

[2] Lee, Charles M., and ellen W. Szeto. "Zipper CMOS". IEEE Circuit and Device Magazine, 8755-3996/86/0500-0010, 1986

[3] Chandrakasan A.P. Sheng S. Brodersen R.W.: "Low-power CMOS digital design" , IEEE Journal of Solid-State Circuits, Volume 27, Issue 4, April 1992 Page(s):473 – 484

[4] Verma N. Kwong J. Chandrakasan A.P.: "Nanometer MOSFET Variation in Minimum Energy Subthreshold Circuits" , IEEE Transactions on Electron Devices, Vol. 55, NO. 1, January 2008 Page(s):163 – 174

[5] Mahmood, Sohail Musa, and Yngvar Berg."Ultra-Low voltage and high speed NP Domino carry propagation chain", 2013 IEEE Faible Tension Consommation, 2013..

[6] K. Kotani, T. Shibata, M. Imai and T. Ohmi. "Clocked-Neuron-MOS Logic Circuits Employing Auto-Threshold-Adjustment", In IEEE International Solid-State Circuits Conference (ISSCC), pp. 320-321,388, 1995.

[7] T. Shibata and T. Ohmi. " A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations", In IEEE Transactions on Electron Devices, vol 39, 1992. [8] Yungvar Berg, Omid Mirmothahari "High Speed and Ultra Low Voltage CMOS NAND and NOR Domino gates " IJECEECE Volumn 6.No.8. 2012

ABSTRACT:Biometric traits are now highly explored by researchers to establish a system that can be used to accurately identify a person. The finger knuckle print refers to the inherent skin patterns that are formed at the joints in the finger back surface. This paper presents techniques used for acquisition and recognition systems based on finger knuckle print. Automatic Knuckle print recognition systems are based on local ridge features known as Minutiae. To select the minutiae points properly and rejecting unwanted ones is very important. The efforts are focused to choose distinctive modality (FKP) for the secure storage and verification of the biometric template for secrete and safety of authentication.

Keywords - Knuckle-print images, knuckle-print recognition, minutiae extraction, ridge bifurcation, ridge ending.,

[1] Lin Hong, Yifei Wan, and Anil Jain, Fingerprint Image Enhancement: Algorithm and Performance Evaluation, IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. 20,August 1998
[2] Osman Yakubu, Osei Adjei, Reliability of Fingerprint Verification in Ghana,International Journal of Computer Applications (0975 – 8887) Volume 107 – No 10, December 2014,pp 9-13.
[3] Mr. Kannan Subramanian, Image Based Fingerprint Verification, International Journal of Innovative Research in Computer and Communication Engineering , Vol. 2, Issue 5, May 2014, pp 4207-4209.
[4] Nadira Quadri#1, Surendra Singh Choudhary, Performance Analysis and Designing of Fingerprints Enhancement Technique Based on Segmentation, OF Estimation and Ridge Frequency, Gabor Filters with Wavelet Transform, International Journal of Computer Science and Information Technologies, Vol. 5 (5) , 2014, 6644-6651.
[5] Roli Bansal, Priti Sehgal and Punam Bedi.,Minutiae Extraction from Fingerprint Images, International Journal of Computer Science Issues,Vol. 8 ,Issue 5 ,no.3,Sept 2011,pp 74-84.

ABSTRACT:Floating point numerical operations being widely used in large set of signal processing computation, scientific, commerce and finance calculation.This implementation involves approach for computing four floating pointnumerical operationswith square root operation also. In top-down design approach, four arithmetic modules: addition/subtraction, multiplication, division, and square root are combined to form a double precision floating point unit.In this paper the proposed design compliant with IEEE-754 format a 64 bit floating point unit is designed which is also handling rounding, overflow, underflow&various exceptions for each operation.Verilog and Questa-Sim design tool used for synthesis and simulation continuously for precise results.

Keywords - Double precision, Floating point unit, Square root, Hardware description language (HDL), IEEE-754

[1] PreethiSudhaGollamudi, M. Kamaraju"‟Design of High Performance IEEE- 754 Single Precision (32 bit) Floating Point Adder Using VHDL‟‟ inInternational Journal of Engineering Research & Technology (IJERT)Vol. 2 Issue 7, July – 2013.
[2] Addankipurna Ramesh,Ch.Pradeep "Fpga Based Implementation of Double PrecisionFloating Point Adder/Subtractor Using Verilog"International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, Volume 2, Issue 7, July 2012).
[3] SARC International Conference, 30th CHAITANYA A. KSHIRSAGAR, P.M. PALSODKAR "An FPGA Implementation of IEEE - 754 Double Precision Floating Point Unit Using Verilog" Proceedings of 4thSARC International Conference, 30th March-2014, Nagpur, India.
[4] Swathi. G. R, Veena. R"Design of IEEE-754 Double Precision Floating Point Unit Using Verilog"in International Journal of Engineering Research & Technology (IJERT)International Journal of Engineering Research & Technology (IJERT)Vol. 3 Issue 4, April – 2014.
[5] KusumaKeerthi "Design of High Performance Single Precision Floating Point Multiplier in (ITSI-TEEE)ISSN (PRINT) 2320 – 8945, Volume -2, Issue -1,2014.