iosr-JEEE   Volume-8 ~ Issue-4

Abstract: This paper explains the design of a simple RISC processor and procedure for simulating it. A Reduced Instruction Set compiler (RISC) is a microprocessor that had been designed to perform a small set of instructions, with the aim of increasing the overall speed of the processor along with reducing the power consuming while executing the instruction. The RISC architecture follows the philosophy that one instruction should be performed every cycle. This work presents the design and implementation of a 32 bit RISC soft core processor intended for computer architecture introduction considered to be an effective solution for computer comprehension. The idea of this project was to create a microprocessor as a building block in VHDL than later easily can be included in a larger design. It will be useful in systems where a problem is easy to solve in software but hard to solve with control logic. A state machine dedicated to the function can of course replace the microprocessor and associated software. However at a high level of complexity it is easier to implement the function in software. In this project Modelsim is used for logical verification and further synthesizing is carried on Xilinx-ISE tool. To perform the power analysis the Xilinx xpower analyzer is used.

Keywords: Low Power, Speed, RISC, Processor, Xilinx.

[1] Pan-Song, Huang-JiYe, SOPC Technology Utility Tutorial, Tsinghua University Press, 2006.
[2] Zheng-WeiMin, Tang-ZhiZhong. Computer System Structure (The second edition), Tsinghua University Press, 2006.
[3] Ramdas, T. Li-Minn Ang and Egan, G., "FPGA implementation of an integer MIPS processor in Handel-C and its application to human face detection," in Proc. of IEEE Region 10 Conference, Vol. 1, pp. 36-39, 2004.
[4] Xizhi Li and Tiecai Li, "ECOMIPS: an economic MIPS CPU design on FPGA," in Proc. of the 4th IEEE International Workshop on System-on- Chip for Real-Time Applications, pp. 291-294, 2004.
[5] D. M. Harris and S. L. Harris, Digital Design and Computer Architecture,1st edition, Morgan Kaufmann, 2007, USA.

Abstract: This paper presents an error detection method with majority logic decoding. The majority logic decodable words are suitable for memory application due to their capability to correct large number of errors, but they require a large decoding time that impacts the memory performance. So in the proposed fault detection method they significantly reduce the memory access time. Keywords: Triple Modular Redundancy, Error Correction Codes, Majority Logic, Low Density parity checks, Difference Set Cyclic Codes, Syndrome Fault Detector, Majority Logic Detector/Decoder.

[1]. E. J. Weldon, Jr., ―Difference-set cyclic codes,‖ Bell Syst. Tech. J., vol.45, pp. 1045–1055, 1966.
[2]. Y. Kato and T. Morita, ―Error correction circuit using difference-set cyclic code,‖ in Proc. ASP-DAC, 2003, pp. 585–586.
[3]. S. Lin and D. J. Costello, Error Control Coding, 2nd ed. Englewood Cliffs, NJ: Prentice-Hall, 2004
[4]. P. Ankolekar, S. Rosner, R. Isaac, and J. Bredow, ―Multi-bit error correction methods for latency-contrained flash memory systems,‖ IEEE Trans. Device Mater. Reliabil., vol. 10, no. 1, pp. 33–39, Mar. 2010.
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[6]. T. Shibuya and K. Sakaniwa, ―Construction of cyclic codes suitable for iterative decoding via generating idempotents,‖ IEICE Trans. Fundamentals, vol. E86-A, no. 4, pp. 928–939, 2003.

Abstract: The binary adder is the critical element in most digital circuit designs including digital signal processors (DSP) and microprocessor data path units. As such, extensive research continues to be focused on improving the power delay performance of the adder. In VLSI implementations, parallel-prefix adders are known to have the best performance. Parallel-prefix adders (also known as carry-tree adders) are known to have the best performance in VLSI designs. This paper investigates three types of carry-tree adders (the Kogge-Stone, sparse Kogge-Stone, and spanning tree adder) and compares them to the simple Ripple Carry Adder (RCA). In this project Xilinx-ISE tool is used for simulation, logical verification, and further synthesizing .

Keywords: DSP, Adders, Delay, Power.

[1] B. Ramkumar and Harish M Kittur , ― Low-Power and Area-Efficient Carry Select Adder ―, IEEE Transactions on very large scale integration (VLSI) systems, vol.20, no.2,pp.371-375, Feb .2012

[2] Dilip P. vasudevan, parag k.lala, james patrik parkerson, ― Self- checking carry-select adder design based on two rail en-coding‖,IEEE Trans, CIRCUITS AND SYSTEMS—I , December 2007

[3] http://en.wikibooks.org/wiki/Digital_Circuits/Adders.html

[4] Yu-Ting Pai and Yu-Kumg Chen, ―The fastest carry look ahead adder,‖ IEEE trans . International Workshop on Electronic Design, Test and Applications,vol.22. Feb .2004

[5] http://umunhum.stanford.edu /farland/notes.html

[6] Dayu Wang, Xiaoping Cui, Xiaojing Wang, ―Optimized design of Parallel Prefix Ling Adder,‖IEEE Trans. pp.941-944, oct.2011 [7] B.Bhaskar, M.Kanagasabapathy, V.S.Kanchana Bhaaskaran, ―A hybrid adiabatic parllel prefix addition scheme for low power‖, IEEE Trans , International Conference on Recent Trends in Information Technology, pp.389-393 , june 2011 [8] G. W. Hanson, Fundamentals of Nanoelectronics. Englewood Cliffs,NJ: Prentice-Hall, 2008.

[9] R. Zhang, K. Walus, W. Wang, and G. A. Jullien, ―Performance comparisonof quantum-dot cellular automata adders,‖ in Proc. IEEE Int. Symp.Circuits Syst., 2005, pp. 2522–2526.

[10] Architecture of FPGAs and CPLDs: A Tutorial - Computer ...www.eecg.toronto.edu/~jayar/pubs/brown/survey.pdfFile Format: PDF/Adobe Acrobat - Quick View.

Abstract: The most noticeable topic for electrical engineering is power quality in recent year. Power quality problem is an occurrence manifested as a nonstandard voltage, current or frequency. Utility distribution networks, sensitive industrial load and critical commercial operation suffer from various types of outages and service interruption can cost significant financial losses. One of the major problems dealt here is the voltage sag.

[1]. Rosli Omar and NasrudinAbd Rahim Faculty of Electrical Engineering, University Teknikal Malaysia Melaka, Malaysia Department of Electrical Engineering , Faculty of Engineering , University of Malaya, Kuala Lumpur, Malaysia "Mitigation of Voltage Sags/Swells Using Dynamic Volt Age Restorer (DVR)" in ARPN Journal of Engineering and Applied Sciences VO L.4,NO. 4, JUNE 2009
[2]. Christoph Meyer , Student Member, IEEE , Rik W. De Doncker , Fellow, IEEE , Yun Wei Li , Member, IEEE , and FredeBlaabjerg, Fellow, IEEE "Optimized Control Strategy for a Medium-Voltage DVR—Theoretical Investigations and Experimental Results" in IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 6, NOVEMBER 2008
[3]. H. Ezoji Electrical & Computer Engineering Department, Babol University of Technology, A. Sheikholeslami, Electrical & Computer Engineering Department, Babol University of Technology, M. Tabasi Electrical & Computer Engineering Department, Babol University of Technology, M.M. Saeednia Electrical & Computer Engineering Department, Babol University of Technology "Simulation of Dynamic Voltage Restorer Using Hysteresis Voltage Control " in European Journal of Scientific Research ISSN 1450-216X Vol.27 No.1 (2009), pp.152-166
[4]. Mahmoud A. El-Gammal Dean of the Faculty of Engineering, Pharos University in Alexandria, Egypt, Amr Y. Abou-Ghazala, Electrical Engineering Dept., Faculty of Engineering, Alexandria University, Egypt, Tarek I. El-Shennawy, Alexandria National Refining and Petrochemicals Co. (ANRPC), Alexandria, Egypt "Dynamic Voltage Restorer (DVR) for Voltage Sag Mitigation" in International Journal on Electrical Engineering and Informatics ‐ Volume 3, Number 1, 2011
[5]. FirouzBadrkhaniAjaei, SaeedAfsharnia, AlirezaKahrobaeian, and ShahrokhFarhangi "A Fast and Effective Control Scheme for the Dynamic Voltage Restorer" in IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 26, NO. 4, OCTOBER 2011
[6]. Michael John Newman,Member, IEEE , Donald Grahame Holmes, Senior Member, IEEE , John Godsk Nielsen, Member, IEEE , and FredeBlaabjerg, Fellow, IEEE "A Dynamic Voltage Restorer (DVR) With Selective Harmonic Compensation at Medium Voltage Level" in IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 41, NO. 6,NOVEMBER/DECEMBER 2005

Abstract: An analog-to-digital converter (abbreviated ADC, A/D or A to D) is a device that converts a continuous quantity to a discrete time digital representation. An ADC may also provide an isolated measurement. The reverse operation is performed by a digital-to-analog converter (DAC). Typically, an ADC is an electronic device that converts an input analog voltage or current to a digital number proportional to the magnitude of the voltage or current. However, some non-electronic or only partially electronic devices, such as rotary encoders, can also be considered ADCs. In order to increase the flexibility of control for ADC, a new control method for ADC based on FPGA is proposed in this paper. A state transition diagram can be drawn according to the timing diagram of ADC, the design is implemented using Very High-speed Integrated Circuit Hardware Description Language (VHDL). The operations of ADC are simulated using the modelsim tool and ADC design is synthesized using Xilinx tool.

[1] Petouris M (Petouris, M.), Kalantzopoulos A (Kalantzopoulos, A.),Zigouris E (Zigouris, E.), "An FPGA-based Digital Camera System Controlled from an LCD Touch Panel" INTERNATIONAL SYMPOSIUM ON SIGNALS, CIRCUITS AND SYSTEMS, pp. 241- 244, 2009.

[2] El-Medany, W.M. ; Hussain, M.R, "A FPGA-based advanced real traffic light controller system design" 007 4th IEEE Workshop on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications, IDAACS, pp. 100-105, 2007.

[3] Guo, Jianmin, Zhang, Ke, Kong, Ming, Li, Wenhong, "Novel ADC architecture for digital voltage regulator module controllers," Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors, v 27, n 12, p 2112-2117,December 2006

[4] Hussein, Aziza I. ,Gruenbacher, Don M.; Ibrahim, Noureddin M , "Design and verification techniques used in a graduate level VHDLcourse," Proceedings - Frontiers in Education Conference, v 2, p 13a4-28 - 13a4-31, 1999.

Abstract: This paper presents a simple step-by-step procedure for the simulation of photovoltaic modules with Matlab/ Simulink as well as Grid connected system for considering Three phase multistring inverter with sinusoidal pulse width modulation control scheme. The single -diode equivalent circuit is employed in order to Investigate I-V and P-V characteristics of a solar module. This paper focuses on a Matlab/SIMULINK model of a photovoltaic cell and Grid connected system, considering three phase multistring inverter with SPWM control scheme to reduce harmonics in primary side and same was applied to grid with prediction of PV cell behaviour under different physical and environmental parameters. The PV model is based on mathematical equations and is described through an equivalent circuit including a photocurrent source, a diode, a series resistor and a shunt resistor. The developed model can also be used to extract the physical parameters for a given solar PV cell as a function of temperature and solar radiation. Three PV strings are cascaded together in parallel configuration and connected to a five-level inverter to produce output voltage in five levels of Vdc. That was equivalent to the amplitude of the triangular carrier signal were used to generate PWM signals for the switches. The inverter offers much less total harmonic distortion and can operate at near-unity power factor.

Keywords: DC-DC Converter, Multilevel Inverter, PV Module, SPWM, proportional–integral (PI) current control, multistring.

[1 ] M.Veerachary, "Power Tracking for Nonlinear PV Sources with Coupled Inductor SEPIC Converter," IEEE Transactions on
Aerospace and Electronic Systems, vol. 41, No. 3, July 2005.
[2] I. H. Altas and A.M. Sharaf, "A Photovoltaic Array Simulation Model for Matlab-Simulink GUI Environment," IEEE, Clean
Electrical Power, International Conference on Clean Electrical Power (ICCEP '07), June 14-16, 2007, Ischia, Italy.
[3] S.Chowdhury, S.P.Chowdhury, G.A.Taylor, and Y.H.Song, "Mathematical Modelling and Performance Evaluation of a Stand-
Alone Polycrystalline PV Plant with MPPT Facility," IEEE Power and Energy Society General Meeting - Conversion and Delivery
of Electrical Energy in the 21st Century, July 20-24, 2008, Pittsburg, USA.
[4] Jee-Hoon Jung, and S. Ahmed, "Model Construction of Single Crystalline Photovoltaic Panels for Real -time Simulation," IEEE
Energy Conversion Congress & Expo, September 12-16, 2010, Atlanta, USA.
[5] S. Nema, R.K.Nema, and G.Agnihotri, "Matlab / Simulink based study of photovoltaic cells / modules / array and their
experimental verification," International Journal of Energy and Environment, pp.487- 500, Volume 1, Issue 3, 2010.
[6] N. A. Rahim and S. Mekhilef, "Implementation of three-phase grid connected inverter for photovoltaic solar power generation
system," in Proc. IEEE PowerCon, Oct. 2002, vol. 1, pp. 570–573.

Abstract: Recently, industry requires the use of static power converters for high voltages and high currents applications. So, it is necessary to use an inverter. Today inverters use high power switching transistors called IGBT's and MOSFETS. These inverters have problems in high power applications. A Stacked Multi-cell Converter (SMC) represents a new solution to the problem. A SMC is an inverter (DC-AC converter) for high voltage applications. Here the analysis of SMC at different levels which decreases the THD with increase in levels is discussed and shown. This topology called SMC (Stacked Multi-cell Converter) consists of a hybrid association of commutation cell making possible to share the voltage and current constraint on several switches and this converter is made up of by p cells and n stacks. This configuration allows to share the total voltage and current stresses among the switches and also to improve the output waveforms of the converter in terms of number of levels and switching frequency. PWM technique is used to control the rms voltage at the output. Then, it is possible to use conventional semiconductors to handle high output power. A closed loop control is proposed using MATLAB Fuzzy Logic Toolbox, to control the RMS voltage at the output.The application area for a SMC can be found in applications such as UPS, Switching Power Supplies, and motor drivers

Keywords: Stacked multi-cell converter, Fuzzy Logic, MATLAB, PWM

[1] M.Carpita, S. Tenconi (1991). A novel multicell structure for voltage source inverter.EPE'1991(Firenze) , Vol. 1, pp90-94.

[2] L. Delmas, G. Gateau, T. A. Meynard, H. Foch "Stacked Multicell converter (SMC): Control and Natural Balancing", Power Electronics Specialists Conference, PESC 02. IEEE 33rd Annual, Vol. 2, 23-27 June 2002, pp. 689 –694.

[3] P. Bhagwat, V.R. Stefanovic, "Generalized structure of a Multilevel PWM inverter", IEEE Industry Applications Society Annual Meeting, pp.761-76, 1980.

[4] Average-Current-Based Conduction Losses Model of Switched Capacitor Converters: Michael Evzelman, Student Member, IEEE, and Shmuel (Sam) Ben-Yaakov, FelloIEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 7, JULY 2013

[5] T. A. Meynard, H. Fosch, Francois Forest, "Multicell Converters: Derived Topologies", IEEE Trans. Ind. This article shows the advantages of the SMC circuit Electron.. Vol. 49, October 2002, pp. 978-987.

[6] G. Gateau, T. A. Meynard, H. Foch. "Stacked Multicell Converter Properties and Design", PESC'20001(Vancouver), Vol. 3, June 17-22, 2001. pp. 1583 –1588.

[7] Earl Cox, "Fuzzy Fundamentals", IEEE Spectrum, October 1992, pp. 58-61.

[8] Kevin Self "Designing With Fuzzy Logic" from IEEE SPECTRUM, November 1990, Volume 105 pp 42-44.

[9] Salvador Revelo Andrade, "Simulación de unConvertidorMultinivelApilableControlado con LógicaDifusa", Master Dissertation, Universidad de las Americas- Puebla, Primavera 2006.

[10] Timothy J. Ross "Fuzzy Logic with Engineering Applications",McGraw Hill, Inc., 1997.

Abstract: A 2.2-kW, 3-phase, 50Hz squirrel-cage induction motor originally designed for 415V(a.c.) application got burnt out from sustained thermal overload. Being that the local supply voltage hardly rises above 380V (a.c.), it had to be refurbished from first principles to reflect this voltage condition. The calculations leading to the choice of the number of poles, number of coils per phase per pole, number of phase groups, number of turns-in-series per phase, amongst other quantities, necessary for the realization of a 380V(a.c.) double-layer lap-type 3-phase stator winding with a diamond overhang were carried out. The method of direct-on-line starting was used to check the workshop performance of the machine. The value of the motor no-load speed was quite satisfactory. It is, however, emphatically recommended that a suitable under-voltage relay-protection scheme be incorporated in the motor power supply system to forestall such breakdown in future.

Keywords: Induction Motor, Refurbishment, Local Voltage Condition.

[1]. Agarwal R. K. (2000): Principles of Electrical Machine Design, 4th Ed., S. K.Kataria & Sons, Delhi.
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[9]. Okoro O. I. (2003): MATLAB Simulation of Induction Machine with Saturable Leakage and Magnetizing Inductances, The Pacific Journal of Science and Technology, Vol.5 No.1, pp5–15, http://www.akamaiuniversity.us/PJST.htm
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Abstract: In micro grids the power management is obtained by energy storage. These changes are being driven from both the demand side where. higher energy availability and efficiency are desired, and from the supply side where the integration of distributed generation and peak-shaving technologies must be accommodated. Distribution systems possessing distributed generation and controllable loads with the ability to operate in both grid-connected and standalone modes are an important class of the so-called Microgrid power system. In this propose work the energy storage capacity varies and raised between the voltage limits, current limits and stability across the power limits.

Keywords: Distributed Generator(DG), transient power flow (TPG), smart grid.

[1] M. Valenti "Reaching for 60 percent, the General Electric H turbine system taking shape in Wales is making a bid for a new record in thermal efficiency." Mechanical Engineering, April 2002. [2] Colleen Williams, "CHP Systems," Distributed Energy, March/April 2004, pp.57-59. [3] Office of Energy Efficiency and Renewable Energy, U.S. Department of Energy, "2001 BTS Core Databook," Office of Building Technology, July 13, 2001 [4] Lasseter, R.," MicroGrids," IEEE PES Winter Meeting, January 2002 [5] Zang, H., M.Chandorkar, G. Venkataramanan, "Development of Static Switchgear for Utility Interconnection in a Microgrid." Power and Energy Systems PES, Feb. 24-26, 2003, Palm Springs, CA. [6] Illindals, M., G. Venkataramanan, "Battery Energy Storage for StandAlone Micro-Source Distributed Generating System," 6th IASTED Intl. Conf. On power and Energy Systems. 2001.

Abstract: In this paper a new topology is proposed for energy storage and the power distribution using Ultra-capacitors in cascaded multilevel inverters. This consists of hybrid cascaded multilevel inverter (HCMI) topologies and corresponding control strategies are applied to motor drive, interfacing both dc sources and capacitor energy storage elements. For high power motor drive application this proposed topology has a capability to produce high voltage at fundamental switching frequency makes it possible to use switches with low voltage and current ratings. The major advantages of this proposed control method are reduced switching loss, improved efficiency with less number of dc sources, elimination of harmonics and the ability of the capacitor voltage to be successfully maintained at the desired value when the machine is in transient state. In this paper a 7-level cascaded multilevel inverter with motor drive is considered. Finally, the simulation results validate the concept of this topology.

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