IOSR Journal of Electronics and Communication Engineering(IOSR-JECE)

Volume 3 - Issue 1

Paper Type : Research Paper
Title : Secure Surveillance Using Virtual Intelligent Agent with Dominating Influence
Country : India
Authors : SINDHU LS , Dr. A. Vishwanath, Mr. U. Arun Kumar
: 10.9790/2834-0310106       logo
Abstract:As it is known embedded system is a special-purpose computer system designed to perform a dedicated function. As a spice we also included robotics domain and achieved this project successfully. In this project, an automation surveillance system is achieved using PIR sensor which detects the human. Also the robot consists of a weapon detector. Once the intruder has been detected, the location will be tracked using GPS and is sent as a message to nearby police station through GSM modem placed .Mean while the robot follows the intruder with the help of ultrasonic and infra red sensor, and a camera is used for capturing the images and transfer it to CCTV.
Keywords-component; weapon detector; automation surveillance;
[1]. Mr. Ashok Kumar MAASTECH PVT ltd, project consultant
[2]. http://chipscity.com/downloads/Projects/GSM%20based%20Control%20System.pdf
[3]. chipscity.com/downloads/.../GSM%20based%20Control%20System.pdf
[4]. www.scribd.com/doc/51358421/GSM-based-ROBOT
[5]. www.circuitstoday.com www.howstuffworks.com
[6]. www.m-indya.com/gsm/gsmarchitecture.php
[7]. www.roggeweck.net/uploads/media/Student_-_GSM_Architecture.pdf
[8]. www.robosapiensindia.com/sat-robotics.php
[9]. www.robosapiensindia.com/sat-robotics.php
[10] .www.celebbest.com

Paper Type : Research Paper
Title : A High Speed Wallace Tree Multiplier Using Modified Booth Algorithm for Fast Arithmetic Circuits
Country : India
Authors : Jagadeshwar Rao M, Sanjay Dubey
: 10.9790/2834-0310711       logo

Abstract: A Wallace tree multiplier using modified booth algorithm is proposed in this paper. It is an improved version of tree based Wallace tree multiplier [1] architecture. This paper aims at additional reduction of latency and power consumption of the Wallace tree multiplier. This is accomplished by the use of booth algorithm, 5:2, 4:2, and 3:2 compressor adders. An efficient VerilogHDL code has been written, successfully simulated and synthesized for Xilinx FPGA vertex-6 low power (Xc6vlx75tl-1Lff484) device, using Xilinx 12.2 ISE and XST. The result shows that the proposed architecture is around 67% faster than the existing Wallace-tree multiplier.
Keywords: Arithmetic, Booth Encoder, Compressors, Radix-8, Wallace-Tree.

[1] C.Vinoth1, V. S. Kanchana Bhaaskaran2, B. Brindha, S. Sakthikumaran, V.Kavinilavu, B.Bhaskar, M. Kanagasabapathy and B. Sharath," A Novel low power and high speed Wallace tree multiplier for risc processor",C 978-1-4244-8679-3/11/$26.00 ©2011 IEEE
[2] Sreehari veeramanchaneni, Kirthi Krishna M, Lingamneni Avinash, Sreekanth Reddy Puppala, and M.B. Srinivas," Novel Architectures for High Speed and Low power 3-2, 4-2 and 5-2 compressors"20th international conference on VLSI Design , jan 2007 , pp. 324-329.
[3] Karuna Prasad and keshab K.Parhi ,"Low Power 4-2 and 5-2 compressors" in proc. of the 35th asilomar conf. on signals, systems and computers,2001, vol. 1, pp.129-133.
[4] Chen Ping-Hua and Zhao Juan , "High speed Parallel 32x32-b Multiplier Using a Radix-16 Booth Encoder".
[5] Weinan Ma, Shuguo Li, "A New High Compression Compressor for Large Multiplier", Institute of Microelectronics,
[6] Tsinghua University, Beijing 100084,P.R. China, 2008 IEEE..
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Paper Type : Research Paper
Title : Real Time Artifact-Free Image Upscaling
Country : India
Authors : G.Ramadevi, T.Mallikarjuna
: 10.9790/2834-0311219       logo
Abstract:Image upscaling (and more generally image interpolation) is the process of resizing a digital image. Enlarging an image is generally common for making smaller imagery fit a bigger screen in full screen mode, for example. In "zooming" an image, it is not possible to discover any more information in the image than already exists, and image quality inevitably suffers, for that reason several methods have been proposed to obtain better results, involving simple heuristics, edge modeling or statistical learning. The most powerful ones, however, present a high computational complexity and are not suitable for real time applications, while fast methods, even if edge-adaptive, are not able to provide artifacts-free images. So that's why a new method for image upscaling is proposed i.e. Iterative Curvature Based Interpolation (ICBI), it is based on a two-step grid filling and an iterative correction of the interpolated pixels obtained by minimizing an objective function depending on the second order directional derivatives of the image intensity. These are implemented in a variety of computer tools like printers, digital TV, media players, image processing packages, graphics renderers and so on.
Keywords - Upscaling, ICBI, NEDI, nVidia CUDA
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[3] S. Battiato, G. Gallo, and F. Stanco. A locally-adaptive zooming algorithm for digital images. Image and Vision Computing, 20:805– 812, 2002.
[4] M.J. Chen, C.H. Huang, and W.L. Lee. A fast edge-oriented algorithm for image interpolation. Image and Vision Computing, 23:791–798, 2005.
[5] R. Fattal. Image up sampling via imposed edge statistics. ACM Transactions on Graphics, 26(3):95, 2007.
[6] W.T. Freeman, T.R. Jones, and E.C. Pasztor. Example-based super resolution. IEEE Computer Graphics and Applications, 22(2):56–65, 2002.
[7] A. Giachetti and N. Asuni. Fast artifact free image interpolation. In Proc. BMVC 2008, 2008.
[8] D. Glasner, S. Bagon, and Michal Irani. Super-resolution from a single image. In proc. 12th International Conference on Computer Vision, pages 349–356. IEEE, 2009.
[9] Kenji Kamimura, Norimichi Tsumura, Toshiya Nakaguchi, Yoichi Miyake, and Hideto Motomura. Video super-resolution using texton substitution. In ACM SIGGRAPH 2007 posters, page 63, New York, NY, USA, 2007. ACM.
[10] K. I. Kim and Y. Kwon. Example-based learning for single-image super resolution. In Proceedings of the 30th DAGM symp. on Patt. Rec., pages 456–465, Berlin, Heidelberg, 2008. Springer-Verlag.

Paper Type : Research Paper
Title : Design of Low Power 2-D Dct Architecture Using Reconfigurable Architecture
Country : India
Authors : Venkata pavan kumar .B, Ch.Venkateswarlu
: 10.9790/2834-0312025       logo
Abstract:This Research paper includes designing a area efficient and low error Discrete Cosine Transform. This area efficient and low error DCT is obtained by using shifters and adders in place of multipliers. The main technique used here is CSD(Canonical Sign Digit) technique.CSD technique efficiently reduces redundant bits. Pipelining technique is also introduced here which reduces the processing time.
1]. Enas Dhuhri Kusuma, Thomas Sri Widodo "FPGA Implementation of Pipelined 2D- DCT and Quantization Architecture for JPEG Image Compression" Proceedings of 978-1-4244-6716-7/10/$26.00 ©2010 IEEE
[2]. Vijay Kumar Sharma, K. K. Mahapatra and Umesh C. Pati "An Efficient Distributed Arithmetic based VLSI Architecture for DCT"
[3]. Chidanandan, Bayoumi, M, "Area-Efficient NEDA Architecture for The 1-D DCT/IDCT" ICASSP 2006 Proceedings. 2006 IEEE International Conference.
[4]. Zhenyu Liu Tughrul Arslan Ahmet T. Erdogan "A Novel Reconfigurable Low Power Distributed Arithmetic Architecture for Multimedia Applications" Proceedings of 1-4244-0630-7/07/$20.00 C 2007 IEEE.
[5]. S.Saravanan, Dr.Vidyacharan Bhaskar, P.T.Lee ,"A High Performance Parallel Distributed Arithmetic DCT Architecture for H.264 Video Compression" European Journal of Scientific Research ISSN 1450- 216X Vol.42 No.4 (2010), pp.558-564 EuroJournals Publishing, Inc. 2010
[6]. VLSI Digital Signal Processing Systems: Design And Implementation (Hardcover) By Keshab K Parhi
[7]. Vijaya Prakash.A.M, K.S.Gurumurthy "A Novel VLSI Architecture for Digital Image Compression Using Discrete Cosine Transform and Quantization", IJCSNS International Journal of Computer Science and Network Security, VOL.10 No.9, September 2010
[8]. Santosh Sanjeevannanavar, Nagamani A.N , "Efficient Design and FPGA Implementation of JPEG Encoder using Verilog HDL" 978-1-4673-0074- 2/11/$26.00 @2011 IEEE 584

Paper Type : Research Paper
Title : RR-MAC: Receiver Reservation MAC Protocol with Time-Division for Wireless Sensor Networks
Country : India
Authors : M. K. Kirubakaran, Dr. N. Shankar Ram
: 10.9790/2834-0312632       logo
Abstract: Wireless sensors networks are potentially employed in various fields such as defense system, target tracking, target monitoring, wildlife monitoring and disaster management. The node's of a wireless sensor network consists of three main parts- processor, transmitter/receiver and memory unit. For these parts to be operational in an efficient way, the battery power of the nodes must be prolonged and utilized effectively. Idle listening, control data overhead, collisions, retransmission are the major problems which reduce the energy efficiency in the nodes.This paper aims at proposing and analyzing RR-MAC protocol (Receiver-Reservation MAC protocol) which uses dynamic multichannel and time division algorithm to enable nodes utilize energy in efficient manner. Further, the idle time is considerably eliminated by adapting a central memory register for making reservations on receivers. The node's will be active only when needed and sleep rest of the time. Collision avoidance and energy loss due to retransmissions are addressed substantially in RR-MAC design. Since the collisions are reduced, the data can be sent with minimized time delay caused by retransmissions.
Keywords: Duty Cycling, Energy Efficiency, Interference, Medium access control, pseudorandom sequence
[1] Rajesh Yadav, Shirshu Varma and N.Malaviya:Optimized Medium Access Control for Wireless Sensor Network,IJCSNS International Journal of Computer Science and Network Security, Vol. 8, No.2, pp. 334 -338 (February 2008).
[2] V. Rajendran, K. Obraczka and J.J. Gracia-Luna-Aceves: Energy Efficient, Collision Free Medium Access Control for Wireless Sensor Networks, in ACM International Conference on Embedded Networked Sensor Systems (SenSys), pp. 181-192 (November 2003).
[3] M.Ali, Saif, A. Dunkels, T. Voigt, K. Romer,K. Langendoen, J. Polastre, Z. A. Uzmi:Medium Access Control Issues in Sensor Networks, ACM SIGCOMM Computer Communication Review, Vol. 36, No. 2 (April 2006).
[4] Joseph Polastre, Jason Hill, and David Culler. Versatile Low Power Media Access for Wireless Sensor Networks. In Proceedings of the Second ACM Conference on Embedded Network Sensor Systems (SenSys 2004), pages 95–107, November 2004.
[5] J. Redi, S. Kolek, K. Manning, C. Partridge, R. Rosales-Hain,R. Ramanathan, and I. Castineyra. JAVeLEN—An Ultra-Low Energy Ad Hoc Wireless Network. Ad Hoc Networks, 6:108–126, January 2008.
[6] Chieh-Jan Mike Liang, Nissanka Bodhi Priyantha, Jie Liu, and Andreas Terzis. Surviving Wi-Fi Interference in Low Power ZigBee Networks. In Proceedings of the 8th ACM Conference on Embedded Network Sensor Systems (SenSys 2010), pages 309–322, November 2010.
[7] Wenyuan Xu, Wade Trappe, Yanyong Zhang, and Timothy Wood. The Feasibility of Launching and Detecting Jamming Attacks in Wireless Networks. In Proceedings of the Sixth ACM International Symposium on Mobile Ad Hoc Networking and Computing(MobiHoc 2005), pages 46–57, May 2005.
[8] Chieh-Jan Mike Liang, Nissanka Bodhi Priyantha, Jie Liu, and Andreas Terzis. Surviving Wi-Fi Interference in Low Power ZigBee Networks. In Proceedings of the 8th ACM Conference on Embedded Network Sensor Systems (SenSys 2010), pages 309–322, November 2010
[9] Tie Luo, Mehul Motani, and Vikram Srinivasan. Cooperative Asynchronous Multichannel MAC: Design, Analysis, and Implementation. IEEE Transactions on Mobile Computing,8(3):338–352, March 2009.
[10] Gang Zhou, Chengdu Huang, Ting Yan, Tian He, John A. Stankovic,and Tarek F. Abdelzaher. MMSN: Multi-Frequency Media Access Control for Wireless Sensor Networks. In Proceedings of the 25th IEEE International Conference on Computer Communications (INFOCOM 2006), pages 1–13, April 2006.

Paper Type : Research Paper
Title : Performance Evolution for Frequency Invariance for Double Differential Detection System
Country : India
Authors : 1SudhaRani karedla, Sri. E.V. Narayana
: 10.9790/2834-0313338       logo
Abstract: The Evolution of Multiple symbol differential detection (MSDD) of double differential QAM signal is studied in the presence of frequency offset ,phase offset and additive white Gaussian noise. It is shown that in the case of nonzero frequency offset distorts the transmitted signal through attenuating its amplitude and MSDD receiver degrades by increases the number of samples. MSDD signal makes use of maximum likehood sequence estimation of transmitted phase rather than the symbol by symbol detection as in the conventional differential detection . It is shown that the proposed receiver is robust to the distortions caused by the random frequency variations and a lower bound on the error probability of the proposed MSDD receiver is also derived .
Keywords-Differential encoding, maximum-likelihood detection, multiple symbol differential detection, Quadrature Amplitude Modulation.
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Paper Type : Research Paper
Title : Optimization of ECAT through DA-DCT
Country : India
Authors : S. Indumathi1 and Dr. M. Sailaja
: 10.9790/2834-0313950       logo
Abstract: Discrete cosine transform (DCT) is a widely used tool in image and video compression applications. Recently, the high-throughput DCT designs have been adopted to fit the requirements of real-time application. Operating the shifting and addition in parallel, an error-compensated adder-tree (ECAT) is proposed to deal with the truncation errors and to achieve low-error and high-speed discrete cosine transform (DCT) design. Instead of the 12 bits used in previous works, 9-bit Distributed Arithmetic was proposed. DA-based DCT design with an error-compensated adder-tree (ECAT) is the proposed architecture in which, ECAT operates shifting and addition in parallel by unrolling all the words required to be computed. Furthermore, the Error-Compensated Circuit alleviates the truncation error for high accuracy design. Based on low-error ECAT, the DA-precision in this work is chosen to be 9 bits instead of the traditional 12 bits. Therefore, the hardware size and cost is reduced, and the speed is improved using the proposed ECAT.
Keywords- Adders, DCT- Discrete Cosine Transform, DA- Distributed Arithmetic, ECAT- Error-Compensated Adder-Tree.
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