IOSR Journal of Computer Engineering (IOSR-JCE)

International conference on Recent Innovations in Engineering (ICRIE'14)

Volume 1

Paper Type : Research Paper
Title : An Approach For Unconstrained Face Recognition Algorithm Using Computer Vision Method
Country : India
Authors : Faizal Y, Konguvel E

Abstract: This address the difficulty of unconstrained face recognition from vaguely acquired images. The main factors that make this difficulty challenging are image dilapidation due to blur, and appearance variations due to illumination and pose. In this paper, we deal with the problems of blur and illumination. We demonstrate the set of all images obtained by blurring a given image forms a convex set. Based on this set theoretic classification, we suggest a blur-robust algorithm whose main step involves solving simple convex optimization troubles. We do not suppose any parametric form for the blur kernels, however, if this information is obtainable , it can be simply integrated into our algorithm..
Keywords – Direct recognition of blurred and illuminated faces, remote biometrics, unconstrained face recognition.

[1] W. Zhao, R. Chellappa, P. J. Phillips, and A. Rosenfeld, "Face recognition: A literature survey," ACM Comput. Surv., vol. 35, no. 4, pp. 399–458, Dec. 2003.
[2] J. Ni and R. Chellappa, "Evaluation of state-of-the-art algorithms for remote face recognition," in Proc. IEEE 17th Int. Conf., Image Process., Sep. 2010, pp. 1581–1584.
[3] M. Nishiyama, A. Hadid, H. Takeshima, J. Shotton, T. Kozakaya, and O. Yamaguchi, "Facial deblur inference using subspace analysis for recognition of blurred faces," IEEE Trans. Pattern Anal. Mach. Intell., vol. 33, no. 4, pp. 838–845, Apr. 2011.
[4] D. Kundur and D. Hatzinakos, "Blind image deconvolution revisited."
[5] A. Levin, Y. Weiss, F. Durand, and W. T. Freeman, "Understanding blind deconvolution algorithms," IEEE Trans. Pattern Anal. Mach. Intell., vol. 33, no. 12, pp. 2354–2367, Apr. 2011.


Paper Type : Research Paper
Title : Randomly Directed Exploration Protocol with Maximum Throughput and Packet Delivery Ratio
Country : India
Authors : Neenu George, T.K.Parani

Abstract:Wireless sensor networks consist a large number of sensor nodes and physical attack suffered by the wireless sensor network is node clone attack. A node clone detection protocol randomly directed exploration is used to detect node clones using forwarding technique based on probability. The simulation is done using NS2 for detection probability, communication cost and storage consumption. An efficient network always is of both security and quality of services. Along with node clone detection the quality of service multicast routing protocol (MQOSPF), is used to provide the quality of services packet delivery ratio and throughput.
Keywords- node clone, NS2, quality of service multicast routing protocol, randomly directed exploration, wireless sensor networks (wsn),

[1]. www.wikipedia.com
[2]. Zhijun Li, Member, IEEE, and Guang Gong, (2013),".On the Node Clone Detection in Wireless Sensor Networks", in proc 5th IEEE transactions,Volume 40,no.11,pp 17-23
[3]. C.Bekara And M.L.Maknavicius(2007),"A new protocol for securing wsn against node replication attacks,"in third IEEE International Conference on wireless and mobile computing, networking and communications,pp59-59
[4]. B. Parno, A. Perrig, and V. Gligor(2005), "Distributed detection of node replication attacks in sensor networks," in Proc. IEEE Symp. Security Privacy, pp. 49–63.
[5]. Zhijun Li And Guang Gong, (2009)"Randomly directed exploration: an efficient node clonedetection protocol in wireless sensor network" ,in proc 5 th IEEE Trans.Volume 11,pp34-4.


Paper Type : Research Paper
Title : A Processor Based Technique with Multi scale Enhancement Algorithm for Extended Interpolation
Country : India
Authors : ArunLal.C.K, Sheela T

Abstract: Through this work, a low complexity and an efficient DWT processor based design is proposed for image scaling application. The paper also introduces a high quality Frequency domain interpolation algorithm for the image scaling. This algorithm consists of a sharpening filter and a smoothing filter. Both the filters act as a pre filters to reduce the blurring and aliasing artifacts produced by the frequency domain technique. To enhance the speed for this proposed system, a serial architecture with partial pipelined structure is introduced along with good utilization in accomplished with resources availability in target FPGA. The new model is designed by System Generator blocks using the simulink Simulation. A Matlab tool along with Xilinx synthesis tool (XST) also used. The final results give the power consumption of 117mW at 28 degree/c in seam temperature. An improvement of speed in 15% with better Signal to noise ratio is obtained from the comparison result.

Keywords -Image Scaling, Frequency Domain, DCT, DFT, DWT.

[1]. Cardells-Tormo. F and Arnabat-Benedicto.A (2006) "Flexible hardware-friendly digital architecture for 2-D separable convolution-based scaling," IEEE Trans. Circuits Syst. II, Exp. Briefs, Volume 53, No. 7, pp. 522–526
[2]. Chen.S.L, Huang.H.Y and Luo.C.H (2011) "A low-cost high-quality adaptive scalar for real-time multimedia applications," IEEE Trans. Circuits Syst.Video Technol., Volume 21, No. 11, pp. 1600–1611.
[3]. Chen. P.Y , Huang .C.C Shiau.Y.H and Chen.Y.T (2009) "A VLSI implementation of barrel distortion correction for wide-angle camera images," IEEE Trans. Circuits Syst. II, Exp. Briefs, Volume 56, No. 1, pp. 51–55.
[4]. Chen.P.Y , Lien.C.Y and Lu.C.P (2009) "VLSI implementation of an edgeoriented image scaling processor," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Volume 17, No. 9, pp. 1275–1284.
[5]. Shih-Lun chen , " VLSI Implementation of a Low–Cost High-Quality Image Scaling Processor",(2013)IEEE Trans. Circuits syst.-II,Exp.Briefs,Volume 60 No.1.


Paper Type : Research Paper
Title : Power Reduction and Glitch free MUX based Digitally Controlled Delay-Lines
Country : India
Authors : MARY PAUL, AMRUTHA. E

Abstract: A wide range MUX based Digitally Controlled Delay Line (DCDL) is presented to achieve low jitter, low power and process immunity. The proposed DCDL have been designed in 90 nm CMOS technology. The proposed MUX based DCDL maintains the same resolution and minimum delay of NAND-based DCDL. In this paper the theoretical demonstration of the glitch-free operation of proposed DCDL is derived. Simulation result shows that novel circuits result in the lowest resolution, with a little worsening of the minimum delay with respect to the previously proposed DCDL with lowest delay. The NAND based DCDL avoid the glitching problem, but the power consumption rate and area will be increased. The proposed MUX based DCDL. Which overcome the limitation by NAND based DCDL.
Keywords- All –digital delay locked loop (ADDLL), all – digital phase locked loop (ADPLL), Control code word, Digitally controlled delay lines (DCDL), Delay –Line.

[1]. R. B. Staszewski, K.Muhammad, D. Leipold, "All-digital TX frequency synthesizer and discrete-time receiver for bluetooth radio in 130-nm CMOS," IEEE J. Solid-State Circuits, Dec. 2004, vol. 39, no. 12, pp. 2278–229.
[2]. R. B. Staszewski and P. T. Balsara"All Digital Frequency Synthesizer in Deep Submicron CMOS" New York: Wiley, 2006.
[3]. R. J. Yang and S. I. Liu, "A 40–550 MHz harmonic-free all digital delay locked loop using a variable SAR algorithm," IEEE J. Solid-State Circuits, Feb. 2007, vol. 42, no. 2, pp. 361–37.
[4]. R. J. Yang and S. I. Liu, "A 2.5 GHz all digital delay locked loop in 0.13 mm CMOS technology," IEEE J. Solid-State Circuits, Nov. 2007, vol. 42, no. 11, pp. 2338–234.
[5]. S. Kao, B. Chen, and S. Liu, "A 62.5–625-MHz anti reset all digital delay locked loop," IEEE Trans. Circuits Syst. II, Exp. Briefs, Jul. 2007,vol. 54, no. 7, pp. 566–57.


Paper Type : Research Paper
Title : Lab Color Space Model with Optical Flow Estimation for Fire Detection in Videos
Country : India
Authors : Arjun Santhosh E, Vinoth E

Abstract: Detecting the breakout of fire rapidly is vital for the prevention of material damage and human casualties. The vision-based flame detection has drawn significant attention in the past decade with camera surveillance systems becoming quite common. Conventional fire detectors use physical sensors to detect fire. However, this may lead to false alarms. In order to prevent false alarms, a computer vision-based fire detection algorithm is developed. In this paper, a new method for identifying fire is proposed .Firstly the RGB image is converted to Lab color space and Optical flow estimation computes correspondence between pixels in the current and the previous frame of an image sequence to detect the moving pixels. Secondly Chan-Vese model is applied for segmentation. Segmentation means partitioning a digital image into multiple segments; Chan-Vese model for active contours is a powerful and flexible method to segment images and here the fire region is segmented. And then a novel fire color model is developed in CIE Lab color space to identify fire pixels. Experimental results show the proposed approach can classify flame and non flame objects, and also has a high time effectiveness.
Keywords – Chan-Vese model, CIE Lab Color Space, Flame Detection, Optical Flow, Segmentation.

[1] T. Chen, P. Wu, and Y. Chiou, "An Early Fire-Detection Method Based on Image Processing," Proc. IEEE Int. Image Process., 2004, pp. 1707-1710.
[2] B.U. Toreyin, Y. Dedeoglu, and A.E. Cetin, "Flame Detection in Video Using Hidden Markov Models," Proc. IEEE Int. Conf. Image Process., 2005, pp. 1230-1233, 2005.
[3] B.U. Toreyin, Y. Dedeoglu, and A.E. Cetin, "Computer Vision Based Method for Real-Time Fire and Flame Detection," Pattern Recognition Lett., vol. 27, no. 1, 2006, pp. 49-58.
[4] T. Celik, H. Demirel, and H. Ozkaramanli, "Automatic Fire Detection in Video Sequences," Proc. European Signal Process. Conf., Florence, Italy, Sept. 2006.
[5] W. Krüll et al., "Design and Test Methods for a Video-Based Cargo Fire Verification System for Commercial Aircraft," Fire Safety J., vol. 41, no. 4, 2006, pp. 290-300.


Paper Type : Research Paper
Title : High Performance Digital Pulsewidth-Control Circuit With Programmable Duty Cycle
Country : India
Authors : Vandana.M, V.Deepika

Abstract: In High speed operations the duty cycle of the clock signal is to bé calibrated at 50%. But the variations in process, voltage and temperature (PVT) influences the duty cycle and make it difficult to calibrate the duty cycle at 50%. To overcome this deviation Pulse width control loops (PWCLs) are used. This work presents a high performance and fast locking all digital pulse width control circuit with programmable duty cycle. For the pulse width control circuit, two delay lines and a time to digital detector is used which reduces the amount of hardware required in the circuit. The output duty cycle is calculated with the help of a new duty cycle setting circuit without the need for a look-up table. The new design is developed in Hardware description language (HDL) to improve the design effort. The pulsewidth-control circuit is capable of operating over a wide frequency range with fewer delay cells. The reliability of the circuit is increased by using a TMR system. Experimental results show that the proposed approach is consuming less area and power when compared with the previous methods and the circuit is reliable.
Keywords – Duty cycle, pulsewidth-control circuit. TMR system, time-to-digital detector

[1]. Jun-Ren Su, Te-Wen Liao and Chung-Chih Hung, "All-Digital fast- locking pulsewidth-control circuit with programmable duty cycle," IEEE Transactions on Very large scale integration (VLSI) systems, vol.21,no. 6, June 2013.
[2]. P. H. Yang and J. S. Wang, "Low-voltage pulsewidth control loops for SoC applications," IEEE J. Solid-State Circuits, vol. 37, no. 10, pp. 1348–1351, Oct. 2002.
[3]. W.-M. Lin and H.-Y. Huang, "A low-jitter mutual-correlated pulsewidth control loop circuit," IEEE J. Solid- State Circuits, vol. 39, No.8, pp. 1366–1369, Aug. 2004.
[4]. Y.-J. Wang, S.-K. Kao, and S.-I. Liu, "All-digital delay- locked loop/pulsewidth-control loop with adjustable duty cycles," IEEE J Solid-State Circuits, vol. 41, no. 6, pp. 1262–1274, Jun. 2006.
[5]. S.-R. Han and S.-I. Liu, "A single-path pulsewidth control loop with a built-in delay-locked loop," IEEE J. Solid-State Circuits, vol. 40, no.5, pp. 1130–1135, May 2005.


Paper Type : Research Paper
Title : SWIFT AND LOW POWER L2 CACHE ARCHITECTURE USING PARTIAL TAG BLOOM FILTER
Country : India
Authors : Arunkumar A K, Boobalan R

Abstract: Today's trend toward high speed as well as low power processors are the development of different level of cache for write through techniqe . To improve the execution time there for decreases the power uses , tag of cache L2 placed in L1 cache ,it reduces the power by 62%. Further decrease of power by partial tag enhanced Bloom filter to improve the accuracy of the cache miss prediction method reduce the tag comparisons of the cache hit prediction method. Here also combine both methods so that their order of application can be dynamically adjusted to adapt to changing cache access behavior, which further reduces execution time. To overcome the common limitation of multistage tag comparison methods . Experimental results showed that the new method reduces the energy consumption of tag comparison by an average of 88.40%, which translates to an average reduction of 35.34% (40.19% with low-power data access) in the total energy consumption of the L2 cache and a further reduction of 8.86% (10.07% with low-power data access) when compared with existing methods.
Keywords - Cache, Bloom filter , power consumption, partial tag, way prediction, way tag

[1]. Dai.J and Wang.L(2009), "Way-tagged cache: An energy efficient L2 cache architecture under write through policy," in Proc. Int. Symp. Low Power Electron. Design.
[2]. Hyunsun Park , Sungjoo Yoo , and Sunggu Lee "A Multistep Tag Comparison Method for a Low-Power L2 Cache" Ieee Transactions On Computer-Aided Design Of Integrated Circuits And Systems, Vol. 31, No. 4, April 2012
[3]. Elham Safi, Andreas Moshovos Andreas Veneris "L-CBF: A Low-Power, Fast Counting Bloom Filter Architecture" IEEE Transactions On Very Large Scale Integration (Vlsi) Systems, Vol. 16, No. 6, June 2008
[4]. Min.R, Jone.W, and Hu.Y(2004), "Location cache: A low-power L2 cache system," in Proc. Int. Symp. Low Power Electron. Design, pp. 120–125.
[5]. Vijaykumar.T.N(2011), "Reactive-associative caches," in Proc. Int. Conf. Parallel Arch. Compiler Tech, p. 4961


Paper Type : Research Paper
Title : Vehicle Detection Based On Feature Extraction and SVM Classification
Country : India
Authors : Colins Antony, Konguvel.E

Abstract: Vehicle detection is very much important in avoiding accidents and for surveillance. Various features are used for the detection of vehicles such as edge detection ,corner detection, color transform, etc. The images background is removed using the Gaussian mixture model(GMM).Afterwards we will extract different features of the images using various methods.The extracted features want to be classified as belonging to vehicle or non vehicle. It is an important process so we go for classification task using the Support Vector Machine (SVM)classification, the process can be termed as the training phase since we are training the image as whether it contains the vehicle features or not. Database of the features of vehicle will be created during the training phase .Same procedure will be followed when we give an input image for the detection purpose such as it will undergo background subtraction using the Gaussian mixture model, the features will be extracted and the extracted features will be compared with trained phase to detect whether there will be vehicle pixel or non vehicle pixel available Using the Haar we can eliminate noise and find corners so as to enhance the detection.
Keywords - Edge Detection,EM GMM,HAAR ,SVM

[1]. R. Lin, X. Cao, Y. Xu, C.Wu, and H. Qiao, ―Airborne moving vehicle detection for video surveillance of urban traffic,ᴧ in Proc. IEEE Intell. Veh. Symp, 2009, pp. 203–208.89
[2]. S. Hinz and A. Baumgartner, ―Vehicle detection in aerial images using generic features, grouping, and context,ᴧ in Proc. DAGM-Symp., Sep. 2001, vol. 2191, Lecture Notes in Computer Science, pp. 45–52.
[3]. J. Y. Choi and Y. K. Yang, ―Vehicle detection from aerial images using local shape information,ᴧ Adv. Image Video Technol., vol. 5414, Lecture Notes in Computer Science, pp. 227–236, Jan. 2009.
[4]. Hoffmann, C., Dang, T., Stiller, ―Vehicle detection fusing 2D visual features,ᴧ IEEE Intelligent Vehicles Symposium, 2004.
[5]. A. C. Shastry and R. A. Schowengerdt, ― Airborne video registration and traffic-flow parameter estimation,ᴧ IEEE Trans. Intell.Transp. Syst., vol. 6, no. 4, pp. 391–405, Dec. 2005


Paper Type : Research Paper
Title : AN ENERGY EFFICIENT ROUTING BASED ON OLSR IN WIRELESS SENSOR NETWORK
Country : India
Authors : N.Nithya, S.Velu chamy M.E, AP/ECE

Abstract: A wireless Sensor Network transfers the data one node to another node, energy efficient manner. An OFDMA method reduced the power conception is independent for Transmitted and Reception. We designed, Optimized link state routing protocol (OLSR).The link state routing protocol. all lump contribute inside an OLSR MANET has to at least fulfill the core functionality while it may implement further enhancements from the auxiliary functions without influencing compatibility with core functionality. Messages corresponding to functions not implemented by this node have to be forwarded in such a way that other nodes that do implement these functions can receive these packets The RFC specifies OLSR as a pure route maintenance protocol which is responsible for determining and maintaining routes but not for actually forwarding data packets. This is supposed to be done by some necessary system. In OLSR all node is known by a "major address" Though a node can have multiple interfaces it is identified by just one of these which is chosen to be the nodes. Finally, minimize the Transmission power using MIMO (Multi-Input and Multi-Output).
Index Terms— Wireless sensor networks, Exterior gate way routing protocol (EGP), MIMO, Optimized Link State (OLSR), Orthogonal Frequency-Division Multiple Access (OFDMA)

[1]. Chi-T sun cheng, (6 June 2013 ), "Delay-Bounded Packet Scheduling Of Bursty Traffic Over Wireless Channels", IEEE Trans. Commun.
[2]. Jay dip Sen, (2, August 2009)"An Efficient Broadcast Authentication Scheme in Wireless Sensor Networks", IEEE Trans. Commun.
[3]. Jay dip Sen, (2, August 2009), "A Survey on Wireless Sensor Network Security", IEEE Trans. Commun.
[4]. Kavitha.T and Sridharan. D, (2010), "Security Vulnerabilities In Wireless Sensor Networks: A Survey", IEEE Trans. Commun.
[5]. Khandani. A, Abounadi. J, Modiano. E, and Zheng. L (Nov2007), "Cooperative routing in static wireless networks," IEEE Trans. Commun., vol. 55, no. 11,


Paper Type : Research Paper
Title : Design Of FFT Using ALU For Efficient OFDM Systems
Country : India
Authors : P.Ramya, J.Sam Suresh

Abstract: In present scenario every process should be efficient and simple. Fast Fourier Transform (FFT) is an efficient algorithm to compute the N point DFT. The main focus of this paper is to design FFT using ALU which is used in receiver blocks of OFDM system. It has greater applications in signal and image processing, communication and instrumentation. But the design of FFT requires large number of additions and complex multiplications. To make this process rapid and simple, the FFT operation should be faster and power efficient. Hence, the 64-point FFT is designed using Arithmetic Logic Unit (ALU).It requires less power compared to the FFT designed using Decimation in Time (DIT) butterfly structure. The design is done in HDL and the synthesized results are analyzed using Xilinx ISE tool.
Keywords- ALU,DIT, FFT,IFFT,OFDM.

[1]. Ahmed Saeed, M.Elbably, G.Abdelfadeel, and M.I.Eladway, "Efficient FPGA Implementation of FFT/IFFT Processor", International Journal of Circuits, Systems and Signal Processing.
[2]. K.Hari Krishna, T.Rama Rao, Vladimir A Labay, "FPGA Implementation of FFT Algorithm for IEEE 802.16e (Mobile WiMax)".International Journal of Computer Theory and Engineering, Vol. 3, No.2 , April 2011.
[3]. Manjunath Lakkannavar, Ashwini Desai, "Design and Implementation of OFDM". International Journal of Engineering and Advanced Technology (IJEAT) Volume 1 Issue 6, August 2012.
[4]. Nilesh Chide, Shreyas Deshmukh, Prof.P.B.Borole "Implementation of OFDM System using IFFT and FFT." International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 3, Issue 1, January February 2013, pp.2009.
[5]. Ashish Raman, Anvesh Kumar And R.K.Sarin "High Speed Reconfigurable FFT Design By Vedic Mathematics" Journal Of Computer Science And Engineering, Volume 1, Issue 1 May 2010


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