iosr-JECE   Volume-8 ~ Issue-5

Abstract: Protocols are commonly used today to connect IP blocks on structured SoCs. Generally Protocol is the back-bone of the SoC and its failure usually leads to a non-functional chip. In present market, various types of standard protocols are available and are used in SoC which requires a bridge to pass the information from one type of protocol to other type of protocol safely and without any data loss.

[1] Clifford E. Cummings, "Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs," SNUG 2001
[2] Chris Spear, "SystemVerilog for Verification, 2nd Edition", Springer, www.springeronline.com, 2008.
[3] Lahir, K., Raghunathan A., Lakshminarayana G., "LOTTERYBUS: a new high-performance communication architecture for system-on-chip deisgns," in Proceedings of Design Automation Conference, 2001.
[4] Sanghun Lee, Chanho Lee, Hyuk-Jae Lee, "A new multi-channel onchip- bus architecture for system-on-chips," in Proceedings of IEEE international SOC Conference, September 2004.
[5] Martino Ruggiero, Rederico Angiolini, Francesco Poletti, Davide Bertozzi, Luca 86
[6] Benini, Roberto Zafalon, "Scalability Analysis of Evolving SoC Interconnect Protocols," Int. Symposium on System-on-Chip, 2004.
[7] Lukai Cai, Daniel Gajski, "Transaction level modeling: an overview," in Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, October 2003.
[8] Min-Chi Tsai, "Smart Memory Controller Design for Video Applications," Master thesis: National Chiao Tung University, July 2006.

Abstract: Speech processing is used widely in every day's applications that most people take for granted, such as network wire lines, cellular telephony, telephony system and telephone answering machines. Due to its popularity and increasing of demand, engineers are trying various approaches of improving the process. One of the methods for improving is trying on different methods of filtering techniques. Thus, this instigates an introduction of a filtering technique known as Kalman filtering. In the early days, Kalman filtering was very popular in the research field of navigation because of its magnificent accurate estimation characteristic. Since then, electronic engineers manipulate its advantages to useful purpose in speech processing. Consequently, today it had become a popular filtering technique for estimating and resolving redundant errors containing in speech.

[1]. Robust adaptive kalman filtering based speech enhancement algorithm by Marcel Gabrea IEEE-2004.
Bibliography
[2]. S. Crisafulli, J.D. Mills, and R.R Bitmead, "Kalman Filtering Techniques in Speech
[3]. Coding". In Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing,
[4]. S. Saito and K. Nakata, "Digitization", Fundamental of Speech Processing"
[5]. C. R. Watkins, "Practical Kalman Filtering in Signal Coding", New Techniques in Signal Coding,
[6]. M.S. Grewal and A.P. Andrews, Kalman Filtering Theory and Practice Using MATLAB.

Abstract: The most effective way to increase the speed of a multiplier is to reduce the number of the partial products because multiplication precedes a series of additions for the partial products. To reduce the number of calculation steps for the partial products, MBA algorithm has been applied mostly where CSA has taken the role of increasing the speed to add the partial products. To increase the speed of the MBA algorithm, many parallel multiplication architectures have been researched. A modified booth multiplier has been designed which provides a flexible arithmetic capacity and a tradeoff between output precision and power consumption due to using of SPST architecture. Moreover, the ineffective circuitry can be efficiently deactivated, thereby reducing power consumption and increasing speed of operation. The experimental results have shown that the proposed multiplier outperforms the conventional multiplier in terms of power and speed of operation. In this paper we used Xilinx-ISE tool for logical verification, and further synthesizing it on Xilinx-ISE tool using target technology and performing placing & routing operation for system verification.

[1] Soojin Kim and Kyeongsoon Cho "Design of High-speed Modified Booth Multipliers Operating at GHz Ranges" World Academy of Science, Engineering and Technology 61 2010.

[2] Magnus Sjalander and Per Larson-Edefors. "The Case for HPM-Based Baugh-Wooley Multipliers," Chalmers University of Technology,Sweden, March 2008.

[3] Z Haung and M D Ercegovac, "High performance Low Power left to right array multiplier design" IEEE rans.Computer, vol 54 no3, page 272-283 Mar 2005.

[4] Aswathy Sudhakar, and D. Gokila, "Run-Time configurable Pipelined Modified Baugh-Wooley Multipliers," Advances in Computational Sciences and Technology ISSN 0973-6107 Volume 3 Number 2 (2010) pp. 223–235.

[5] Myoung-Cheol Shin, Se-Hyeon Kang, and In-Cheol Park, "An Area-Efficient Iterative Modified-Booth Multiplier Based on Self-Timed Clocking," Industry, and Energy through the project System IC 2010, and by IC Design Education Center (IDEC).

[6] Leandro Z. Pieper, Eduardo A. C. da Costa, Sérgio J. M. de Almeida, "Efficient Dedicated Multiplication Blocks for2´s Complement Radix-2m Array Multipliers," JOURNAL OF COMPUTERS, VOL. 5, NO.10, OCTOBER 2010.

[7] Wen-Chang Yeh and Chein-Wei Jen, "High-speed Booth encoded parallel multiplier design," IEEE Trans. on Computers, vol. 49, isseu 7,pp. 692-701, July 2000.

[8] Jung-Yup Kang and Jean-Luc Gaudiot, "A simple high-speed multiplier design," IEEE Trans. on Computers, vol. 55, issue 10, Oct. pp.1253-1258, 2006.