iosr-JECE   Volume-8 ~ Issue-3

Abstract: The Motion Estimation Computing Array is used in Video Encoding applications to calculate the best motion between the current frame and reference frames. The MECA is in decoding application occupies large amount of area and timing penalty. By introducing the concept of Built-in Self test technique the area overhead is increased in less amount of area. In this Paper the Built-in Self test Technique (BIST) is included in the MECA and in each of Processing Element in MECA is tested using residue codes .the quotient and remainder was cross checked across the processing element and test code generator. further the residue code is replaced with the boolen logic adder in trst code generator in order to reduce the area of the circuit.Thus by introducing the BIST Concept the testing is done internally without Connecting outside testing Requirements. So the area required is also reduces. And in this Project the Errors in MECA are Calculated and the Concept of Diagnoses i.e. Self Detect and Self Repair Concepts are introduced.

Keywords: Data recovery, error detection, motion estimation, reliability, residue-and-quotient (RQ) code.

[1] Chun-lung Hsu, chang-Hsin Cheng, and Yu Liu, "Built- in self-detection/correction Architecture for Motion Estimation Computing Arrays", IEEE Transcations on Very Large Scale Integration (VLSI) systems, VOL.18, NO.2, February 2010, pp.319-324.
[2] Thammavarapu R.N Rao, Member, IEEE, "Biresidue Error-Correcting Codes for Computer Arithmetic", IEEE Transactions on computers, VOL. C-19, NO. 5, May 1970, pp.398-402.
[3] Meihua GU, Ningmei YU, Lei ZHU, Wenhua JIA, "High Throughput and Cost Efficient VLSI Architecture of Integer Motion Estimation for H.264/AVC", Journal of Computational Information Systems 7:4 (2011), pp.1310-1318.
[4] Zhong-Li He, Chi-Ying Tsui, Member, IEEE, Kai-Keung Chan, and Ming L. Liou, Fellow, IEEE, "Low-Power VLSI Design for Motion Estimation Using Adaptive Pixel Truncation", IEEE Transactions on circuits and systems for video technology, VOL.10, NO.5, August 2000, pp.669- 677.
[5] R. J. Higgs and J. F. Humphreys, "Two-error-location for quadratic residue codes," Proc. Inst. Electr.Eng. Commun, vol. 149, no. 3, Jun.2002, pp.129–131.
[6] T. H. Wu, Y. L. Tsai, and S. J. Chang, "An efficient design-for-testability scheme for motion estimation in H.264/AVC," in Proc. Int. Symp. VLSI Design, Autom. Test, Apr. 2007, pp. 1–4.
[7] M. Y. Dong, S. H. Yang, and S. K. Lu, "Design-for-testability techniques for motion estimation computing arrays," in Proc. Int. Conf. Commun., Circuits Syst., May 2008, pp. 1188–1191.
[8] Y. S. Huang, C. J. Yang, and C. L. Hsu, "C-testable motion estimation design for video coding systems," J. Electron. Sci. Technol., vol. 7, no. 4, pp. 370–374, Dec. 2009.
[9] D. Li, M. Hu, and O. A. Mohamed, "Built-in self-test design of motion estimation computing array," in Proc. IEEE Northeast Workshop Circuits Syst., Jun. 2004, pp. 349–352.

Abstract: In the deep sub micrometer CMOS process technology, the interconnect resistance, length, and inter-wire capacitance are increasing significantly, which contribute to large on-chip interconnect propagation delay. Data transmitted over interconnect determine the propagation delay and the delay is very significant when adjacent wires are transitioning in opposite directions (i.e., crosstalk transitions) as compared to transitioning in the same direction. Propagation delay across long on-chip buses is significant when adjacent wires are transitioning in opposite direction (i.e., crosstalk transitions) as compared to transitioning in the same direction. By exploiting Fibonacci number system, we propose a family of Fibonacci coding techniques for crosstalk avoidance, relate them to some of the existing crosstalk avoidance techniques, and show how the encoding logic of one technique can be modified to generate code words of the other technique.

Keywords: On-chip bus, crosstalk, Fibonacci coding.

[1] S.P. Khatri "Cross-talk Noise Immune VLSI Design using Regular Layout Fabrics", PhD thesis, University of California at Berkeley, Berkeley, California, 1999.

[2] S.P. Khatri, A. Mehrotra, R.K. Brayton, Ralf H.J.M. Otten, and A.L. Sangiovanni-Vincentelli. "A novel vlsi layout fabric for deep sub-micron applications", In Proceedings of Design Automation Conference, pages 491–496. IEEE, 1999.

[3] F. Caignet, S. Delmas-Bendhia, and E. Sicard, "The challenge of signal integrity in deep-submicrometer CMOS technology," Proc. IEEE, vol. 89, no. 4, pp. 556–573, Apr. 2001.

[4] D. Pamunuwa, L.-R. Zheng, and H. Tenhunen, "Maximizing throughput over parallel wire structures in the deep submicrometer regime," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 11, no. 2, pp. 224–243, Apr. 2003.

[5] R. Arunachalam, E. Acar, and S. Nassif, "Optimal shielding/spacing metrics for low power design," in Proc. IEEE Comput. Soc. Annu. Symp. VLSI, 2003, pp. 167–172.

[6] B. Victor and K. Keutzer, "Bus encoding to prevent crosstalk delay," in Proc. IEEE/ACM Int. Conf. Comput.-Aided Design, 2001, pp. 57–63.

[7] C. Duan, A. Tirumala, and S. Khatri, "Analysis and avoidance of crosstalk in on-chip buses," in Proc. Hot Interconnects, 2001, pp. 133–138.

[8] P. Subramanya, R. Manimeghalai, V. Kamakoti, and M. Mutyam, "A bus encoding technique for power and cross-talk minimization," in Proc. IEEE Int. Conf. VLSI Design, 2004, pp. 443–448. [9] M. Stan and W. Burleson, "Limited-weight codes for low power I/O," in Proc. IEEE/ACM Int. Workshop Low Power Design, 1994, pp. 209–214.

[10] M. Mutyam, "Preventing crosstalk delay using Fibonacci representation," in Proc. IEEE Int. Conf. VLSI Design, 2004, pp. 685–688.

Abstract: Energy optimization is a prime issue in wireless sensor network that consumes less energy to give optimum performance under low battery power, limited bandwidth and network life time of each node. In this paper, first we investigate and analyze three network layer protocols, centralized, localized, bellman ford(distributive) and next we develop a new algorithm called bellman ford asynchronous sleep wake up protocol for energy saving in packet transmission and to prolong the network lifetime. The simulation results on metrics energy spent, throughput, average delay and product delivery ratio confirms that the new protocol outperforms the other protocols.

Keywords: Localized, Centralized, Distributed, Asynchronous Sleep Wake Up.

[1] *Ivan Stojmenovic, University of Ottawa, Localized Network Layer Protocols In Wireless Sensor Networks Based on Optimizing Cost over progress Ratio,IEEE Networks 2006
[2] Low Power, Low Delay:Opportunistic Routing meets Duty Cycling- Olaf Landsiedel_ 1, Euhanna Ghadimi2, Simon Duquennoy3, Mikael Johansson2 olafl@chalmers.se, euhanna@kth.se, simonduq@sics.se, mikaelj@kth.se i)Chalmers University of Technology, Sweden ii)KTH Royal Institute of Technology, Sweden iii)Swedish Institute of Computer Science (SICS), Sweden

[3] C. Huang, F. Dai, and J. Wu, "On-Demand Location-Aided QoS Routing in Ad Hoc Networks," Proc. Int'l. Conf. Parallel Proc., Montreal, Canada, Aug. 2004.

[4] T. He et al., "A Spatiotemporal Communication Protocol for Wireless Sensor Networks," IEEE Int'l. Conf. Distrib. Comp. Sys., May 2003; to appear, IEEE Trans. Parallel and Distrib. Sys

[5] I. Stojmenovic, A. Nayak, and J. Kuruvila, "Design Guidelines for Routing Protocols in Ad Hoc and Sensor Networks with a Realistic Physical Layer," IEEE Commun. Mag., Ad Hoc and Sensor Networks Series, vol. 43, no. 3, Mar. 2005, pp. 101–06.

[6] I. Stojmenovic and X. Lin, "Power Aware Localized Routing In Ad Hoc Networks," IEEE Trans. Parallel and Distrib. Sys., vol. 12, no. 10, Oct. 2001, pp. 1023–32.

[7] M. R. Souryal, B. R. Vojcic, and R. L. Pickholtz, "Information Efficiency of Multihop Packet Radio Networks with Channel-Adaptive Routing," IEEE JSAC, vol. 23, no. 1, 2005, pp. 40–50.

[8] M. Mauve et al., "Position-Based Multicast Routing for Mobile Ad Hoc Networks," TR-03-004, Dept. Comp. Sci., Univ. of Mannheim, Mar. 2003; ACM Mobihoc Poster, 2003.

[9] P. M. Ruiz and I. Stojmenovic, "Cost-efficient Multicast Routing in Ad Hoc and Sensor Networks," to appear, Handbook on Approximation Algorithms and Metaheuristics, T. Gonzalez, Ed., Chapman & Hall/CRC.