iosr-JECE   Volume-7 ~ Issue-2

Abstract: Normally fire detection system uses the heuristic fixed threshold values in their specific methods. However, input images may be changed, in general, so the heuristic fixed threshold values used in the fire detection systems might be modified on a case by case basis. In this paper, an automatic fire detection system without the heuristic fixed threshold values was studied. We presented an automatic method using the statistical color model and the binary background mask. We did the experiment using 600 frames from 6 typical different fire video clips. As the experimental results the proposed method showed a good performance of about average 85% detection rate without false positive, compared with the other methods with the heuristic fixed threshold values.

Keywords: Emperical value,Fire detection,RGB,threshold,sensors

[1] Korean National Emergency Management Agency, Analysis Report of Fire Occurrence in January in 2007, 2007.

[2] Podrzaj and H. Hashimoto, "Intelligent Space as a Framework for Fire detection and Evaluation," Fire Technology, 2007.

[3] T.-H.(C.-H.) Chen, P.-H. Wu, and Y.-C. Chiou, "An Early Fire-Detection Method Based on Image Processing," International Conference on Image Processing, pp. 1707-1710, 2004.

[4] B.-M. Lee and Dongil Han, "Real-Time Fire Detection Using Camera Sequence Image in Tunnel Environment," Proceedings of ICIC, vol. 4681, pp. 1209-1220, 2007.

[5] T. Celik, H. Demirel, H. Ozkaramanli, and M. Uyguroglu, "Fire Detection using Statistical Color Model in Video Sequences," Journal of Visual Communication & Image Representation, vol. 18, pp.176-185,2007.

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[7] B.U. Toreyin, Y. Deleoglu, U. Gudukbay, and A.E. Cetin, "Computer Vision Based Method for Real-time Fire Detection," Pattern Recognition Letter, vol. 27, pp. 49-58, 2006.

[8] Darko Stipanicev, Tomislav Vuko, Damir Krstinic, Maja Stula and Ljiljana Bodrozic, "Forest Fire Protection byAdvanced Video Detection System - Croatian Experiences,"Workshop on Improvement of Disaster Management Systems - local and global trends Trogir : RCADR Divulje ,2006.

Abstract: Network on Chip has emerged as new paradigm for the system designers to design an on chip interconnection network. However, NOC presents a large amount of array of design parameters and decision that are sometimes difficult to tackle. Apart from these issues NOC presents a framework of communication for complex SOC and has been widely accepted by the industries and academia's. Today all the complex VLSI circuitry which requires an on chip communication between them are the part of NOC. The mature concepts of communication network such as routing algorithm, switching technique, flow and congestion control etc in the NOC are the important features on which the performance of NOC depends. This paper introduces the efficient source routing algorithm which generates the minimum hop from source to destination. Performance of NOC network in terms of latency and throughput for minimum hop source routing algorithm is also evaluated.

Keywords: Network on chip, routing algorithm, topology, traffic.

[1] Wang Zhang, Ligang Hou, Jinhui Wang, Shuqin Geng, Wuchen Wu in "Comparison Research between XY and Odd-Even Routing Algorithm of a 2-D 3X3 Mesh topology Network-on-Chip.

[2] Ge-Ming Chiu "The Odd Even Turn Model for Adaptive Routing" in IEEE Transaction on Parallel and Distributed System, Vol.11 No.7, July 2012.

[3] Andres Mejia, Maurizio Palesi, Jose Flich, Shashi Kumar "Region Based Routing: A Mechanism to Support Efficient Routing Algorithms in NOCs" in IEEE Transactions on VLSI System, Vol.17, No.3, March 2009.

[4] Haibo Zhu,Partha Pratim Pande, Cristian Grecu in "Performance Evaluation of Adaptive Routing Algorithms for achieving Fault Tolerance in NoC Fabrics" in IEEE transaction 2007. [5] Wei Luo and Dong Xiang "An Efficient Adaptive Deadlock Free Routing Algorithm for Torus Networks", in IEEE Transaction on Parallel And Distributed System, Vol. 23 No.5,May 2012.

[6] Ran Manevich et al. in "Centralized Adaptive Routing for NoCs" IEEE Computer Architecture Letters, Vol. 9, NO. 2, July-December 2010.

[7] Jose Flich and Jose Duato in "Logic Based Distributed Routing for NoCs" in IEEE Computer Architecture Letter, Vol.7, No. 1, January-June 2008.

[8] Lalit Kishore Arora, Rajkumar "Simulation and Analysis of Packet loss in Mesh Interconnection Networks" National Conference on Development of Reliable Information Systems, Techniques and Related Issues (DRISTI) 2012 Proceedings published in International Journal of Computer Applications® (IJCA) .

[9] M. Mirza-Aghatabar+,S.Koohi+, S. Hessabi*, M. Pedram†An "Empirical Investigation of Mesh and Torus NoC Topologies Under Different Routing Algorithms and Traffic Models" Sharif University of Technology, Tehran, Iran,

[10] Kanchan Manna, Santanu Chattopadhayay and Indranil Sen Gupta "Energy and Performance Evaluation of a Dimension Order Routing Algorithm for Mesh-of-Tree based Networks-on –Chip Architecture" in Annual IEEE India Conference 2010.

Abstract: In this paper, a highly area-efficient multiplier-less FIR filter is presented. Distributed Arithmetic (DA) has been used to implement a bit-serial scheme of a general asymmetric version of an FIR filter, taking optimal advantage of the 3-input LUT-based structure of FPGAs. The implementation of FIR filters on FPGA based on traditional arithmetic method costs considerable hardware resources, which goes against the decrease of circuit scale and the increase of system speed. This paper presents the realization of area efficient architectures using Distributed Arithmetic (DA) for implementation of Finite Impulse Response (FIR) filter. The performance of the bit-serial and bit parallel DA along with pipelining architecture with different quantized versions are analyzed for FIR filter Design. Distributed Arithmetic structure is used to increase the resource usage while pipeline structure is also used to increase the system speed. In addition, the divided LUT method is also used to decrease the required memory units. However, according to Distributed Arithmetic, we can make a Look-Up-Table (LUT) to conserve the MAC values and callout the values according to the input data if necessary. Therefore, LUT can be created to take the place of MAC units so as to save the hardware resources. The simulation results indicate that FIR filters using Distributed Arithmetic can work stable with high speed and can save almost 50 percent hardware resources to decrease the circuit scale, and can be applied to a variety of areas for its great flexibility and high reliability. This method not only reduces the LUT size, but also modifies the structure of the filter to achieve high speed performance.

Keywords: DSP, Digital Filters, FIR , FPGA, MAC, Distributed Arithmetic(DA),Divided LUT, pipeline

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