Volume-7 ~ Issue-1
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| Paper Type | : | Research Paper |
| Title | : | Enhancing Digital Cephalic Radiography |
| Country | : | India |
| Authors | : | S. Venkatakiran, C. Kumar |
| : | 10.9790/2834-0710104 ![]() |
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Abstract: We present a new algorithm, called the soft-tissue filter that can make both soft and bone tissue clearly visible in digital cephalic radiographies under a wide range of exposures. It uses a mixture model made up of two Gaussian distributions and one inverted lognormal distribution to analyze the image histogram. The image is clustered in three parts: background, soft tissue, and bone using this model. Improvement in the visibility of both structures is achieved through a local transformation based on gamma correction, stretching, and saturation, which is applied using different parameters for bone and soft-tissue pixels. A processing time of 1 s for 5 M pixel images allows the filter to operate in real time. Although the default value of the filter parameters is adequate for most images, real-time operation allows adjustment to recover under- and overexposed images or to obtain the best quality subjectively. The filter was extensively clinically tested: quantitative and qualitative results are reported here
Index Terms: Digital radiography, histogram-based clustering, image enhancement, local gamma correction,
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[5] D.-C. Chang and W.-R. Wu, "Image contrast enhancement based on ahistogram transformation of local standard deviation," IEEE Trans. Med.Imag., vol. 17, no. 8, pp. 518–531, Aug. 1998.
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Abstract: OFDM is a modulation as well as multiplexing technique which is widely used in various high speed mobile and wireless communication systems because of its capacity of ensuring high level robustness against interference. In this paper the design and implementation of OFDM system along with SLM implementation to reduce PAPR[6]is illustrated and a detailed simulation of the OFDM system with 16-QAM. OFDM transceiver is implemented using FPGA Spartan6 kit. The hardware results show a detailed study of RTL schematics and Test Bench. In this paper, the software simulation results show 2dB reduction in the peaks.
Keywords - Field Programmable Gate Array, Matlab Simulink, Orthogonal Frequency Division Multiplexing , Peak-to-Average Power Ratio, Selective level Mapping and Xilinx
[1] Mathuran Athan "Simulation of OFDM system in Matlab – BER Vs Eb/N0 for OFDM in AWGN channel" Gaussian Waves, http://www.gaussianwaves.com 2011/07/simulation-of-ofdm-system-in-matlab-ber-vs-ebn0-for-ofdm-in-awgn-channel/
[2] Zoha Pajoudi and Sied Hamidreza Jamali "Hardware Implementation of a 802.11n MIMO OFDM Transceiver", International Symposium on Telecommunications, 2008, pp. 414-419
[3] Yu Wei Lin and Chen Yi Lin, "Design of FFT/IFFT Processor for MIMO OFDM Systems", IEEE Transaction on circuit and system, vol. 54, no. 4, pp. 807-815, 2007
[4] Ashok Jhunjhunwala, "Next Generation wireless for rural areas", Indian Journal of Radio and Space Physics, vol. 36, pp. 165-167, 2007
[5] K. C. Chang and Gerald E. Sobelman "FPGA Based Design of a Pulsed-OFDM system," IEEE APCCAS ,2006, pp. 1128-1131
[6] N.V Irukrulapati,V.K Chakka and A. Jain "SLM based PAPR reduction of OFDM signal using new phase sequence",electronic letters, vol45 No24, 2009.
[7] V.Vijayarangam,R.Kalidoss, Dr.(Mrs)R.Sukanesh "LCM for PAPR Reduction in OFDM systems", ICWMMN Proceedings, 2006.
[8] N.V Irukulapati, V.KChakka and A.Jain "SLM based PAPR reduction of OFDM signal using new phase sequence" electronic letters, vol 45 No.24.
[9] Xiaowen Gu, Seungmin Baek, Suwon Park ,"PAPR Reduction of OFDM Signal Using an Efficient SLM Technique, 2007, LTE Solution Department, Shanghai Huawei Technologies Co., Ltd, Shanghai, China
[10] R. van Nee and A. deWild, "Reducing the peak to average power ratio of OFDM," in Proceedings of the 48th IEEE Semiannual Vehicular Technology Conference, May 1998, vol. 3, pp. 2072–2076.
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| Paper Type | : | Research Paper |
| Title | : | Area Time Efficient Scaling Free Rotation Mode Cordic Using Circular Trajectory |
| Country | : | India |
| Authors | : | N. Hima bindu, K. Geetha |
| : | 10.9790/1676-0711220 ![]() |
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Abstract: This paper presents an area-time efficient Coordinate Rotation Digital Computer (CORDIC) algorithm that completely eliminates the scale-factor. Besides we have proposed an algorithm to reduce the number of CORDIC iterations by increasing the number of stages. The efficient scale factor compensation techniques are proposed which adversely effect the latency/throughput of computation. The proposed CORDIC algorithm provides the flexibility to manipulate the number of iterations depending on the accuracy, area and latency requirements. The CORDIC is an iterative arithmetic algorithm for computing generalized vector rotations without performing multiplications.
Index Terms: coordinate rotation digital computer (CORDIC), cosine/sine, field-programmable gate array (FPGA), most-significant-1, recursive architecture, Discrete Fourier Transform (DFT), Discrete Cosine transform (DCT), Iterative CORDIC, Pipelined CORDIC.
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Process., vol. 81, pp. 1813–1822, 2001.
[3] P. K. Meher, J.Walls, T.-B.Juang, K. Sridharan, and K. Maharatna, "50 years of CORDIC: Algorithms, architectures and
applications," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 9, pp. 1893–1907, Sep. 2009.
[4] C. S. Wu and A. Y. Wu, "Modified vector rotational CORDIC (MVRCORDIC) algorithm and architecture," IEEE Trans. Circuits
Syst. II, Exp. Briefs, vol. 48, no. 6, pp. 548–561, Jun. 2001.
[5] C.-S.Wu, A.-Y.Wu, and C.-H. Lin, "A high-performance/low-latency vector rotational CORDIC architecture based on extended
elementary angle set and trellis-based searching schemes," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process, vol. 50, no.
9, pp. 589 601, Sep.2003.
[6] Y. H. Hu and S. Naganathan, "An angle recoding method for CORDIC algorithm implementation," IEEE Trans. Compute., vol. 42,
no. 1, pp. 99–102, Jan. 1993.
[7] M. G. B. Sumanasena, "A scale factor correction scheme for the CORDIC algorithm," IEEE Trans. Compute., vol. 57, no. 8, pp.
1148–1152, Aug. 2008.
[8] J. Villalba, T. Lang, and E. L. Zapata, "Parallel compensation of scale factor for the CORDIC algorithm," J. VLSI Signal Process.
Syst., vol. 19, no. 3, pp. 227–241, Aug. 1998.
[9] L. Vachhani, K. Sridharan, and P. K. Meher, "Efficient CORDIC algorithms and architectures for low area and high throughput
implementation," IEEE Trans. Circuit Syst. II, Exp. Briefs, vol. 56, no. 1, pp. 61–65,Jan. 2009.
[10] K. Maharatna, S. Banerjee, E. Grass, M. Krstic, and A. Troya, "Modified virtually scaling-free adaptive CORDIC rotator algorithm
and architecture,"IEEE Trans. Circuits Syst. Video Technol., vol. 11, no. 11,pp. 1463–1474, Nov. 2005.
