iosr-JECE   Volume-6 ~ Issue-5

Abstract: In any computing environment, it is necessary for the processor to have fast accessible RAM that allows temporary storage of data. DDR3- SODIMM module is a key component in the memory interface and is becoming increasingly important in enabling higher speeds. Considering higher bandwidths and speeds more than 1GHz, DDR3 is enabling poses more and more high speed signaling and design challenges. Characterized SODIMM module need to be designed to understand and analyze the impact of SODIMM parameters at higher speeds and thereby define more robust memory interface. This will include simulation, board design, validation and results correlation and involves high speed simulation and validation methodologies.

Keywords – Validation, Correlation, DDR3, Characterized SODIMM, Signal Integrity

[[1] Li, P. ; Martinez, J. ; Tang, J. ; Priore, S. ; Hubbard, K. ;Jie Xue ; Poh, E. ; Ong MeiLin ; Chok KengYin ; Hallmark, C. ;Mendez, D.
Development and evaluation of a high performance fine pitch SODIMM socket package, 1161 - 1166 Vol.1, IEEE,2004.
[2] PC3-6400/PC3-8500/PC3-10600/PC3-12800 DDR3 Un buffered SO-DIMM Reference Design Specification, Revision 0.71 draft.
[3] JEDEC STANDARD DDR3 SDRAM Specification (Revision of JESD79-3A, September 2007).
[4] PCB design tutorial and Orcad capture user guide.
[5] Infiniium DSO80000B Series Oscilloscopes and InfiniiMax Series Probes 2 GHz to 13 GHz Real -time Oscilloscope Measurement
Systems data sheet.
[6] Infiniium Series Oscilloscope Probes, Accessories, and Options Selection Guide Data Sheet.
[7] 1168A and 1169A InfiniiMax Differential and Single-ended Probes user guide.
[8] HSPICE® Simulation and Analysis User Guide Version Z-2007.03, March 2007.
[9] HSPICE Signal Integrity Guide U-2003.03-PA, March 2003.

Abstract: This paper presents the design exploration of a spurious-power suppression technique (SPST) which can dramatically reduce the power dissipation of combinational VLSI designs for multimedia/DSP purposes. The proposed SPST separates the target designs into two parts, i.e., the most significant part and least significant part (MSP and LSP), and turns off the MSP when it does not affect the computation results to save power. The objective of a good multiplier is to provide a physically compact, good speed and low power consuming chip. To save significant power consumption of a VLSI design, it is a good direction to reduce its dynamic power that is the major part of total power dissipation. In this paper, we propose a high speed low-power multiplier adopting the new SPST implementing approach. This multiplier is designed by equipping the Spurious Power Suppression Technique (SPST) on a modified Booth encoder which is controlled by a detection unit using an AND gate. The modified booth encoder will reduce the number of partial products generated by a factor of 2. The SPST adder will avoid the unwanted addition and thus minimize the switching power dissipation.

Keywords-Booth encoder; low power; spurious power suppression technique(SPST); SPST-Adder.

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Abstract: In any computing environment, it is necessary for the processor to have fast accessible RAM that allows temporary storage of data. DDR3- SODIMM module is a key component in the memory interface and is becoming increasingly important in enabling higher speeds. Considering higher bandwidths and speeds more than 1GHz, DDR3 is enabling poses more and more high speed signaling and design challenges. Characterized SODIMM module need to be designed to understand and analyze the impact of SODIMM parameters at higher speeds and thereby define more robust memory interface. This will include simulation, board design, validation and results correlation and involves high speed simulation and validation methodologies.

Keywords – Validation, Correlation, DDR3, Characterized SODIMM, Signal Integrity

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