Volume-5 ~ Issue-2
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| Paper Type | : | Research Paper |
| Title | : | New Fault Injection Approach for Network on Chip |
| Country | : | India |
| Authors | : | Tapas Patel |
| : | 10.9790/2834-0520106 ![]() |
Abstract: Packet-based on-chip interconnection networks, or Network-on-Chips (NoCs) are progressively
replacing global on-chip interconnections in Multi-processor System-on-Chips (MP-SoCs) thanks to better
performances and lower power consumption. However, modern generations of MP-SoCs have an increasing
sensitivity to faults due to the progressive shrinking technology. Consequently, in order to evaluate the fault
sensitivity in NoC architectures, there is the need of accurate test solution which allows to evaluate the fault
tolerance capability of NoCs. This paper presents an innovative test architecture based on a dual-processor
system which is able to extensively test mesh based NoCs. The proposed solution improves previously developed
methods since it is based on a NoC physical implementation which allows to investigate the effects induced by
several kind of faults thanks to the execution of on-line fault injection within all the network interface and router
resources during NoC run-time operations. The solution has been physically implemented on an FPGA platform
using a NoC emulation model adopting standard communication protocols. The obtained results demonstrated
the effectiveness of the developed solution in term of testability and diagnostic capabilities and make our
solutions suitable for testing large scale NoC design.
Micro, Vol. 25, No. 6, pp. 10-16, November 2005.
[2] L. Chunsheng, V. Iyengar, S. Jiangfan, E. Cota, "Power- Aware Test Scheduling in Network-on-Chip Using Variable-Rate On Chip
Clocking", IEEE International Very Large Scale of Integration Test Symposium , 2005, pp. 349 – 354
[3] B. Vermeulen, J. Dielissen, K. Goossens, C. Ciordas, "Bringing communications networks on a chip: test and verification
implications", IEEE Communications Magazine, Volume 41, Septmber, 2003, pp. 74 – 81.
[4] A. Kohler, G. Schley, M. Radetzki, "Fault Tolerant Network on Chip Switching With Graceful Performance Degradation", IEEE
Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 29, No. 6, June 2010, pp. 883 – 896.
[5] M. Nahvi, A. Ivanov, "Indirect Test Architecture for SoC Testing", IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems, Volume 23, Issue 7, July 2004, pp. 1128 – 1142.
[6] Xilinx Product Specification, "LogiCORE IP XPS HIWCAP", Product Spec., DS586, June 22, 2011.
[7] T. Bjerregaard and S. Mahadevan, "A survey of research and practices of network -on-chip", ACM Computing Surveys, Vol. 38, pp. 1-51, March, 2006.
[8] J. Duato, S. Yalamanchili, L. Ni, "Interconnection Networks – An Engineering Approach", Morgan Kaufmann, 2002.
[9] C. Grecu, P. Pande, A. Ivanov, R. Saleh, "Timing Analysis of Network -on-chip Architectures for MP-SoC Platforms", Elsevier
Microelectronics Journa, XX
[10] L. Benini, D. Bertozzi, "Xpipes: A Network-on-chip architecture for gigascale systems-on-chip", IEEE Circuits and Systems
Magazine, Volume 4, Issue 2, 2004, pp. 18-31.
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| Paper Type | : | Research Paper |
| Title | : | Use of Smart Antennas In Ad Hoc Networks |
| Country | : | India |
| Authors | : | N. Sudhakar Reddy, Dr. Bhattacharya |
| : | 10.9790/2834-0520710 ![]() |
Abstract: The capacity of ad hoc networks can be severely limited due to interference constraints. One way of
using improving the overall capacity of ad hoc networks is by the use of smart antennas. Smart antennas allow
the energy to be transmitted or received in a particular direction as opposed to disseminating energy in all
directions. This helps in achieving significant spatial re-use and thereby increasing the capacity of the network.
However, the use of smart antennas presents significant challenges at the higher layers of the protocol stack. In
particular, the medium access control and the routing layers will have to be modified and made aware of the
presence of such antennas in order to exploit their use. In this paper we examine the various challenges that
arise when deploying such antennas in ad hoc networks and the solutions proposed thus far in order to
overcome them. The current state of the art seems to suggest that the deployment of such antennas can have a
tremendous impact in terms of increasing the capacity of ad hoc networks.
[2] MSC1210 - Precision Analog-to-Digital Converter (ADC) with 8051 Microcontroller and flash Memory - Texas Instruments
[3] www.vegenotrix.com
[4] Preliminary Design on the Development of Wireless Sensor Network for Paddy Rice ropping Monitoring Application in Malaysia by Muhamad Azman Miskam, Azwan bin Nasirudin from European Journal of Scientific Research
[5] Use of Enzymatic Biosensors as Quality Indices: A Synopsis of Present and Future Trends in The Food Industry from Chilean Journal of Agricultural Research 69(2):270-280 (April-June2009)
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| Paper Type | : | Research Paper |
| Title | : | Implementation of Robots in Spot Welding Process |
| Country | : | India |
| Authors | : | Mrs Magar J.E, Prof.Shelkikar R.P |
| : | 10.9790/2834-0521114 ![]() |
Abstract: Within industry many repetitive operations, such as pick and place, spot welding, and spraypainting, have been successfully automated. While the operations themselves are diverse, a common thread within nearly all of them is that the robot performing the task. From a control perspective, this means that the robot need only be controlled to follow a desired task.Robots are well-established in the material processing industry. They are used for cutting, welding and marking of work pieces made from diverse materials. In these applications it is important to move the focal spot of the welding exactly along the desired machining contour on the work piece. Due to their mechanical inertia, robot arms can not perform abrupt changes of velocity (direction and magnitude) even though this is frequently required in machining operations. In this paper a automation technique is proposed, which is intended to partly overcome the limitations of doing the same work by using manpower. The paper describes control strategy ,which is based on plc automation and a real time interface to a standard robot controller. Simulation-based and experimental results are presented and the performance of the control strategy in various test scenarios is described.
Key Words: Automation Control, ,Programmable logic control Robotics and Automation,Robotic assembly.
rodná konferencia , Mechanika z .67, Modulowe technologie i konstrukcje w budowie maszyn , Rzeszóv 2006, Polsko, str. 261-
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