iosr-JECE   Volume-4 ~ Issue-1

Abstract: The purpose of my project is to design & simulate the frequency divider using ADS software. My project is totally emphasized on the IEEE 802.11 a standard. The IEEE 802.11a describes the WLAN standard. The basis of the project is the SCL (Source Coupled Logic). This thesis organization provides an overview of the evolution of digitally programmable FREQUENCY DIVIDER using CMOS technology.
Keywords:Dual Modulus Prescaler, OFDM, RS Latch, SCL, Swallow Counter.

[1] Christopher Lam and Behzad Razavi, Member, IEEE " 2.6-GHz/5.2-GHz Frequency Synthesizer in 0.4-m CMOS Technology".
[2] Masoud Zargari, Member, IEEE, David K. Su, Member, IEEE, C. Patrick Yue, Member, IEEE, "A 5-GHz CMOS Transceiver for
IEEE 802.11a Wireless LAN Systems ".
[3] Alexandre Marsolaist, Mourad N. El-Gamal1, and Mohamad Sawan"Department of Electrical & Computer Engineering, McGill
University, Canada "A CMOS. Frequency Synthesizer Covering the Lower and Upper Bands of 5GHz WLANs".
[4] B. Razavi, "Design considerations for direct-conversion receivers," IEEE Trans. Circuits Syst. II, vol. 44, pp. 428–435, June 1997.
[5] I. Bouras et al., "A Digitally Calibrated 5.15-5.825GHz Transceiver for 802.11a Wireless LANs in 0.18μm CMOS".
[6] P. Zhang et al., "A Direct Conversion CMOS Transceiver for IEEE 802.11a WLANs,"

Abstract:Finite impulse response (FIR) filters are widely used in various DSP applications. The low-power or low-area techniques developed specifically for digital filters can be found in. Many applications in digital communication (channel equalization, frequency channelization), speech processing (adaptive noise cancelation), seismic signal processing (noise elimination), and several other areas of signal processing require large order FIR filters ,since the number of multiply-accumulate (MAC) operations required per filter output increases linearly with the filter order, real-time implementation of these filters of large orders is a challenging task. This paper presents the methods to reduce dynamic power consumption of a digital Finite Impulse Response (FIR) filter these methods include low power serial multiplier and serial adder, combinational booth multiplier, shift/add multipliers, folding transformation in linear phase architecture and applied to fir filters to power consumption reduced thus reduce power consumption due to glitches is also reduced. This paper is implemented using XILINX ISE and hardware used is Spartan-3E and family is XC2S200E.
Keywords: Digital Filters, DSP, FIR, FPGA, Multipliers.

[1] Huang, Z. and M.D. Ercegovac, 2002. Signal gating for low-power array multiplier design. In: IEEE International Symposium on
Circuits and Systems, ISCAS‟2002, IEEE Computer Society, Washington DC., USA, pp: 489 -492. Doi:
10.1109/ISCAS.2002.1009884.
[2] Manish Bhardwaj, R. Min and A.P. Chandrakasan, 2001. Quantifying and enhancing power awareness of VLSI systems. IEEE
Trans. VLSI Syst.,9: 757-772.
[3] Meier, P.C.H., R.A. Rutenber and L.R. Carley,1999. Inverse polarity techniques for highspeed/low-power multipliers. In:
International Symposium on Low Power Electronics and Design, ISLPEAD‟1999, IEEE Computer Society,Washington DC., USA,
pp: 264-266.
[4] Kim, S. and M.C. Papaefthymiou, 2000.Reconfigurable low energy multiplier formultimedia system design. In: Proceedings of
IEEEComputer Society Workshop on VLSI, 2000, IEEEComputer Society, Washington DC., USA,pp: 129-134. Doi:
10.1109/IWV.2000.844541.
[5] Sinha, A., A. Wang and A. Chandrakasan, 2002. Energy scalable system design. IEEE Trans. VLSI Syst., 10: 135-145.
[6] Di, J., J.S. Yuan and R.F. DeMara, 2006.Improving power-awareness of pipelined array multipliers using 2-dimensional pipeline
gating and its application to FIR design. Integration the VLSI Journal.,39(2):9 112.doi:10.1016/j.vlsi.2004.08.2
[7] Di, J. and J.S. Yuan, 2003. Power-aware pipelined multipliers design based on 2-dimensional pipeline gating, Proceedings of 13th
ACM Great Lakes Symposium on VLSI 2003,Washington, DC, USA, 64-67.
[8] Hoang, Q.D., B.R. Zeydel and V.G. Oklobdzija, 2006. Energy optimization of pipelined digital systems using circuit sizing and
supply scaling. IEEE Trans. VLSI Syst., 14: 122-134.
[9] Lee, K.H. and C.S. Rim, 2000. A hardware reduced multiplier for low power design. In: Proceedings of the 2nd IEEE Asia-Pacific
Conference on ASICs, 2000, IEEE Computer Society, Washington DC., USA, pp: 331-334. Doi: 10.1109/APASIC.2000.896975.
[10] Parhi, K.K., 1999. VLSI Digital Signal Processing Systems. John Willey and Sons Inc., USA.

Abstract:Single hopping is implemented by using software approach over IEEE802.11WLAN card using orthogonality concept and protocol. Most feature of single hopping is to achieve virtual Wi-Fi network. Design parameters of this approach are time delay and energy consumption .There are many scenarios where a wireless device connect to virtual Wi-Fi network. In this paper we improve the energy consumption and reduce the switching delay over popular IEEE 802.11 WLAN and present the performance of virtual Wi-Fi for single hop ad hoc network in terms of delay and energy consumption. Finally we approached multihopping in an ad hoc network using channelization with node synchronization.
Keywords: Wi-Fi, ad hoc network, IEEE 802.11.

[1] Ranveer Chandra, Christ of Fetzer and Karin Hogstedt. Proceedings of Informatics, 1st International Conference on Ad-hoc
Networks and Wireless, Toronto, Vol. 16, pp 1-16, September 20-22, 2002. P. Barford and M. Crovella.
[2] ATA Flash Memory Cards. http://www.magicram.com/flshcrd.htm.
[3] The ethereal network analyzer. http://www.ethereal.com/.
[4] Relatek. http://www.realtech.com.tw/
[5] VMware: Enterprise-Class Virtualization Software. http://www.vmware.com/.
[6] WildPackets Airopeek. http://www.wildpackets.com/products/airopeek.
[7] Paul Barford and Mark Crovella. Generating Representative Web Workloads for Network and Server Performance Evaluation. In
ACM SIGMETRICS 1998, pages 151–160, July 1998.
[8] Josh Broch, David A. Maltz, and David B. Johnson. Supporting Hierarchy and Heterogeneous Interfaces in Multi-Hop Wireless Ad
Hoc Networks. In Workshop on Mobile Computing held in conjunction with the International Symposium on Parallel Architectures,
June 1999.
[9] E. Bugnion, S. Devine, and M. Rosenblum. Disco: Running Commodity Operating Systems on Scalable Multiprocessors. In
Sixteenth ACM Symposium on Operating System Principles, October 1997.
[10] Martin Heusse, Franck Rousseau, Gilles Berger-Sabbatel, and Andrzej Duda. Performance Anomaly of 802.11b. In IEEE
INFOCOM, 2003.