iosr-JECE   Volume-18 ~ Issue-2 ~ Mar. - Apr. 2023

Abstract:Cognitive Radio system is a smart wireless communication system that can sense the radio spectrum and detect unused spectrum holes. CR is an application of SDR. CR involves four stages i.e., spectrum sensing, spectrum decision, spectrum sharing and spectrum mobility. In this project Matched filter, Energy detection and Compressive sensing are implemented. These techniques are coded in MATLAB Software. Energy detection method is one of the most commonly used signal sensing methods in spectrum sensing due to its low implementation complexity. It is a simple technique as it does not require prior knowledge about the primary user signal. The primary goal of spectrum sensing is to identify empty spectrum gaps across broad frequency ranges so that secondary users can use them to fulfil their needs. However, sensing process requires a great deal of time, compressive sensing is used to speed up the spectrum sensing..

Keywords: Cognitive radio, Spectrum sensing, Matched filter, Energy Detection, Compressive spectrum sensing, Threshold, SNR, PFA, PD.

[1]. Yanqueleth Molina-Tenorio, Alfonso Prieto-Guerrero and Rafael Aguilar-Gonzalez, "Real-Time Implementation of Multiband Spectrum Sensing Using SDR Technology". IEEE Access 2021.
[2]. Youness Arjoune and Naima Kaabouch, "Wideband Spectrum Sensing: A Bayesian Compressive Sensing Approach" 2018.
[3]. Ashish Ranjan, Anurag and Balwinder singh, "Design and Analysis of Spectrum Sensing in Cognitive Radio based on Energy Detection" 2016.
[4]. Ulversoy, "Software Defined Radio: Challenges and Opportunities". IEEE Commun. Surv. Tutor. 2010, 12, 531–550

Abstract: Reduction of computational costs can be achieved effectively by approximate computing. With this approach, the circuit's power use, latency, and area are traded off against computational precision. For various applications, the accuracy requirements could change, never the less. In some circumstances, precise outcomes are necessary. In order to compute accurate or approximate results, we used the construction of the radix-4 adder using domino logic. As we take reference circuit of radix-4 adder with 2 2 bit adders are to be added. This circuit includes the combination of AND gates, OR gates, NOR gates and XOR gates. This reference circuit has three outputs and five.......

Key Word: Domino Logic, Radix 4 Adder, Approximate Computing, Computational costs, Precision

[1]. Dr. Savita Sonoli, Basavarajeshwari K V, "A low power accuracy- configurable radix-4 adder using 8T XOR gate",vol7, IJRTI, ISSN:2456-3315, May 2022
[2]. V. Gupta, D. Mohapatra, A. Raghunathan and K. Roy, "Low-power digital signal processing using approximate adders", IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 32, no. 1, pp. 124-137, May.2016.
[3]. Mariano Aguirre-Hernandez and Monico Linares-Aranda, "CMOS Full-Adders for EnergyEfficient Arithmetic Applications", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 4, pp. 718-721, Apr. 2011.
[4]. B. Ramkumar and Harish M. Kittur, "Low-Power and Area-Efficient Carry Select Adder", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 2, pp. 371-375, Feb. 2012.
[5]. Shahzad Asif and Mark Vesterbacka, "Performance analysis of radix-4 adders", Integration the VLSI Journal, vol. 45, no. 2, pp. 111-120, Mar. 2012.

Abstract: Background: Nonlinear functions like the discrete wavelet transform (DWT) and discrete cosine transform (DCT) are frequently used in digital signal processing techniques. The speed of addition and multiplication operations has a significant impact on the speed and accuracy of these calculations. The critical path of the entire system may be impacted by multipliers, which typically have the longest delay among basic operational blocks. The modified radix-4 Booth's algorithm (MBA) is frequently used to achieve high-speed multiplication. These designs and algorithms can be used in application with the Xilinx 12.3i tool as well as the Verilog language. Booth recoding is a strategy for reducing the amount of incorrect products.......

Key Word: Booth recoding, partial products, XOR-based implementation, Fused add multiply operator, carry select adder, Xilinx 12.3i, Verilog

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